69 static int fsl_pcie_check_link(struct pci_controller *hose)  in fsl_pcie_check_link()  argument
73 	if (hose->indirect_type & PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK) {  in fsl_pcie_check_link()
74 		if (hose->ops->read == fsl_indirect_read_config)  in fsl_pcie_check_link()
75 			__indirect_read_config(hose, hose->first_busno, 0,  in fsl_pcie_check_link()
78 			early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val);  in fsl_pcie_check_link()
82 		struct ccsr_pci __iomem *pci = hose->private_data;  in fsl_pcie_check_link()
96 	struct pci_controller *hose = pci_bus_to_host(bus);  in fsl_indirect_read_config()  local
98 	if (fsl_pcie_check_link(hose))  in fsl_indirect_read_config()
99 		hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;  in fsl_indirect_read_config()
101 		hose->indirect_type &= ~PPC_INDIRECT_TYPE_NO_PCIE_LINK;  in fsl_indirect_read_config()
117 static void setup_swiotlb_ops(struct pci_controller *hose)  in setup_swiotlb_ops()  argument
120 		hose->controller_ops.dma_dev_setup = pci_dma_dev_setup_swiotlb;  in setup_swiotlb_ops()
125 static inline void setup_swiotlb_ops(struct pci_controller *hose) {}  in setup_swiotlb_ops()  argument
196 static void setup_pci_atmu(struct pci_controller *hose)  in setup_pci_atmu()  argument
198 	struct ccsr_pci __iomem *pci = hose->private_data;  in setup_pci_atmu()
218 	if (of_device_is_compatible(hose->dn, "fsl,bsc9132-pcie")) {  in setup_pci_atmu()
231 	if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {  in setup_pci_atmu()
250 		if (!(hose->mem_resources[i].flags & IORESOURCE_MEM))  in setup_pci_atmu()
253 		paddr_lo = min(paddr_lo, (u64)hose->mem_resources[i].start);  in setup_pci_atmu()
254 		paddr_hi = max(paddr_hi, (u64)hose->mem_resources[i].end);  in setup_pci_atmu()
257 		offset = hose->mem_offset[i];  in setup_pci_atmu()
258 		n = setup_one_atmu(pci, j, &hose->mem_resources[i], offset);  in setup_pci_atmu()
262 			hose->mem_resources[i].flags |= IORESOURCE_DISABLED;  in setup_pci_atmu()
268 	if (hose->io_resource.flags & IORESOURCE_IO) {  in setup_pci_atmu()
274 				 (u64)hose->io_resource.start,  in setup_pci_atmu()
275 				 (u64)resource_size(&hose->io_resource),  in setup_pci_atmu()
276 				 (u64)hose->io_base_phys);  in setup_pci_atmu()
277 			out_be32(&pci->pow[j].potar, (hose->io_resource.start >> 12));  in setup_pci_atmu()
279 			out_be32(&pci->pow[j].powbar, (hose->io_base_phys >> 12));  in setup_pci_atmu()
282 				| (ilog2(hose->io_resource.end  in setup_pci_atmu()
283 				- hose->io_resource.start + 1) - 1));  in setup_pci_atmu()
292 		pr_err("%pOF: No outbound window space\n", hose->dn);  in setup_pci_atmu()
297 		pr_err("%pOF: No space for inbound window\n", hose->dn);  in setup_pci_atmu()
302 	early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, 0xffffffff);  in setup_pci_atmu()
303 	early_read_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, &pcicsrbar_sz);  in setup_pci_atmu()
311 	early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, pcicsrbar);  in setup_pci_atmu()
315 	pr_info("%pOF: PCICSRBAR @ 0x%x\n", hose->dn, pcicsrbar);  in setup_pci_atmu()
333 	reg = of_get_property(hose->dn, "msi-address-64", &len);  in setup_pci_atmu()
338 			pr_info("%pOF: extending DDR ATMU to cover MSIIR", hose->dn);  in setup_pci_atmu()
343 				"unsupported\n", hose->dn, address);  in setup_pci_atmu()
351 	if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {  in setup_pci_atmu()
357 					"greater than memory size\n", hose->dn);  in setup_pci_atmu()
370 		hose->dma_window_base_cur = 0x00000000;  in setup_pci_atmu()
371 		hose->dma_window_size = (resource_size_t)sz;  in setup_pci_atmu()
404 			pr_info("%pOF: Setup 64-bit PCI DMA window\n", hose->dn);  in setup_pci_atmu()
437 		hose->dma_window_base_cur = 0x00000000;  in setup_pci_atmu()
438 		hose->dma_window_size = (resource_size_t)paddr;  in setup_pci_atmu()
441 	if (hose->dma_window_size < mem) {  in setup_pci_atmu()
447 			 hose->dn);  in setup_pci_atmu()
454 				hose->dn);  in setup_pci_atmu()
456 		pr_info("%pOF: DMA window size is 0x%llx\n", hose->dn,  in setup_pci_atmu()
457 			(u64)hose->dma_window_size);  in setup_pci_atmu()
461 static void __init setup_pci_cmd(struct pci_controller *hose)  in setup_pci_cmd()  argument
466 	early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd);  in setup_pci_cmd()
469 	early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd);  in setup_pci_cmd()
471 	cap_x = early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX);  in setup_pci_cmd()
476 		early_write_config_word(hose, 0, 0, pci_x_cmd, cmd);  in setup_pci_cmd()
478 		early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);  in setup_pci_cmd()
484 	struct pci_controller *hose = pci_bus_to_host(bus);  in fsl_pcibios_fixup_bus()  local
496 		is_pcie = early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP);  in fsl_pcibios_fixup_bus()
497 	no_link = !!(hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK);  in fsl_pcibios_fixup_bus()
499 	if (bus->parent == hose->bus && (is_pcie || no_link)) {  in fsl_pcibios_fixup_bus()
507 				par = &hose->io_resource;  in fsl_pcibios_fixup_bus()
509 				par = &hose->mem_resources[i-1];  in fsl_pcibios_fixup_bus()
522 	struct pci_controller *hose;  in fsl_add_bridge()  local
553 	hose = pcibios_alloc_controller(dev);  in fsl_add_bridge()
554 	if (!hose)  in fsl_add_bridge()
558 	hose->parent = &pdev->dev;  in fsl_add_bridge()
559 	hose->first_busno = bus_range ? bus_range[0] : 0x0;  in fsl_add_bridge()
560 	hose->last_busno = bus_range ? bus_range[1] : 0xff;  in fsl_add_bridge()
565 	pci = hose->private_data = ioremap(rsrc.start, resource_size(&rsrc));  in fsl_add_bridge()
566 	if (!hose->private_data)  in fsl_add_bridge()
569 	setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,  in fsl_add_bridge()
573 		hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK;  in fsl_add_bridge()
575 	if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {  in fsl_add_bridge()
577 		hose->ops = &fsl_indirect_pcie_ops;  in fsl_add_bridge()
579 		early_read_config_byte(hose, 0, 0, PCI_HEADER_TYPE, &hdr_type);  in fsl_add_bridge()
585 		early_read_config_byte(hose, 0, 0, PCI_CLASS_PROG, &progif);  in fsl_add_bridge()
591 	setup_pci_cmd(hose);  in fsl_add_bridge()
594 	if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {  in fsl_add_bridge()
595 		hose->indirect_type |= PPC_INDIRECT_TYPE_EXT_REG |  in fsl_add_bridge()
597 		if (fsl_pcie_check_link(hose))  in fsl_add_bridge()
598 			hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;  in fsl_add_bridge()
613 		    !early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX)) {  in fsl_add_bridge()
614 			early_read_config_word(hose, 0, 0,  in fsl_add_bridge()
617 			early_write_config_word(hose, 0, 0,  in fsl_add_bridge()
624 		(unsigned long long)rsrc.start, hose->first_busno,  in fsl_add_bridge()
625 		hose->last_busno);  in fsl_add_bridge()
628 		hose, hose->cfg_addr, hose->cfg_data);  in fsl_add_bridge()
632 	pci_process_bridge_OF_ranges(hose, dev, is_primary);  in fsl_add_bridge()
635 	setup_pci_atmu(hose);  in fsl_add_bridge()
638 	setup_swiotlb_ops(hose);  in fsl_add_bridge()
643 	iounmap(hose->private_data);  in fsl_add_bridge()
645 	if (((unsigned long)hose->cfg_data & PAGE_MASK) !=  in fsl_add_bridge()
646 	    ((unsigned long)hose->cfg_addr & PAGE_MASK))  in fsl_add_bridge()
647 		iounmap(hose->cfg_data);  in fsl_add_bridge()
648 	iounmap(hose->cfg_addr);  in fsl_add_bridge()
649 	pcibios_free_controller(hose);  in fsl_add_bridge()
683 	struct pci_controller *hose = pci_bus_to_host(bus);  in mpc83xx_pcie_exclude_device()  local
685 	if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK)  in mpc83xx_pcie_exclude_device()
692 	if (bus->number == hose->first_busno ||  in mpc83xx_pcie_exclude_device()
693 			bus->primary == hose->first_busno) {  in mpc83xx_pcie_exclude_device()
699 		if (ppc_md.pci_exclude_device(hose, bus->number, devfn))  in mpc83xx_pcie_exclude_device()
709 	struct pci_controller *hose = pci_bus_to_host(bus);  in mpc83xx_pcie_remap_cfg()  local
710 	struct mpc83xx_pcie_priv *pcie = hose->dn->data;  in mpc83xx_pcie_remap_cfg()
721 	if (bus->number == hose->first_busno)  in mpc83xx_pcie_remap_cfg()
737 	struct pci_controller *hose = pci_bus_to_host(bus);  in mpc83xx_pcie_write_config()  local
740 	if (offset == PCI_PRIMARY_BUS && bus->number == hose->first_busno)  in mpc83xx_pcie_write_config()
752 static int __init mpc83xx_pcie_setup(struct pci_controller *hose,  in mpc83xx_pcie_setup()  argument
778 	WARN_ON(hose->dn->data);  in mpc83xx_pcie_setup()
779 	hose->dn->data = pcie;  in mpc83xx_pcie_setup()
780 	hose->ops = &mpc83xx_pcie_ops;  in mpc83xx_pcie_setup()
781 	hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK;  in mpc83xx_pcie_setup()
786 	if (fsl_pcie_check_link(hose))  in mpc83xx_pcie_setup()
787 		hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;  in mpc83xx_pcie_setup()
802 	struct pci_controller *hose;  in mpc83xx_add_bridge()  local
855 	hose = pcibios_alloc_controller(dev);  in mpc83xx_add_bridge()
856 	if (!hose)  in mpc83xx_add_bridge()
859 	hose->first_busno = bus_range ? bus_range[0] : 0;  in mpc83xx_add_bridge()
860 	hose->last_busno = bus_range ? bus_range[1] : 0xff;  in mpc83xx_add_bridge()
863 		ret = mpc83xx_pcie_setup(hose, &rsrc_reg);  in mpc83xx_add_bridge()
867 		setup_indirect_pci(hose, rsrc_cfg.start,  in mpc83xx_add_bridge()
873 	       (unsigned long long)rsrc_reg.start, hose->first_busno,  in mpc83xx_add_bridge()
874 	       hose->last_busno);  in mpc83xx_add_bridge()
877 	    hose, hose->cfg_addr, hose->cfg_data);  in mpc83xx_add_bridge()
881 	pci_process_bridge_OF_ranges(hose, dev, primary);  in mpc83xx_add_bridge()
885 	pcibios_free_controller(hose);  in mpc83xx_add_bridge()
890 u64 fsl_pci_immrbar_base(struct pci_controller *hose)  in fsl_pci_immrbar_base()  argument
894 		struct mpc83xx_pcie_priv *pcie = hose->dn->data;  in fsl_pci_immrbar_base()
918 		pci_bus_read_config_dword(hose->bus,  in fsl_pci_immrbar_base()
1036 	struct pci_controller *hose;  in is_in_pci_mem_space()  local
1040 	list_for_each_entry(hose, &hose_list, list_node) {  in is_in_pci_mem_space()
1041 		if (!(hose->indirect_type & PPC_INDIRECT_TYPE_EXT_REG))  in is_in_pci_mem_space()
1045 			res = &hose->mem_resources[i];  in is_in_pci_mem_space()
1149 	struct pci_controller *hose = dev_id;  in fsl_pci_pme_handle()  local
1150 	struct ccsr_pci __iomem *pci = hose->private_data;  in fsl_pci_pme_handle()
1162 static int fsl_pci_pme_probe(struct pci_controller *hose)  in fsl_pci_pme_probe()  argument
1171 	dev = list_first_entry(&hose->bus->devices, typeof(*dev), bus_list);  in fsl_pci_pme_probe()
1178 	pme_irq = irq_of_parse_and_map(hose->dn, 0);  in fsl_pci_pme_probe()
1185 	res = devm_request_irq(hose->parent, pme_irq,  in fsl_pci_pme_probe()
1188 			"[PCI] PME", hose);  in fsl_pci_pme_probe()
1196 	pci = hose->private_data;  in fsl_pci_pme_probe()
1214 static void send_pme_turnoff_message(struct pci_controller *hose)  in send_pme_turnoff_message()  argument
1216 	struct ccsr_pci __iomem *pci = hose->private_data;  in send_pme_turnoff_message()
1235 static void fsl_pci_syscore_do_suspend(struct pci_controller *hose)  in fsl_pci_syscore_do_suspend()  argument
1237 	send_pme_turnoff_message(hose);  in fsl_pci_syscore_do_suspend()
1242 	struct pci_controller *hose, *tmp;  in fsl_pci_syscore_suspend()  local
1244 	list_for_each_entry_safe(hose, tmp, &hose_list, list_node)  in fsl_pci_syscore_suspend()
1245 		fsl_pci_syscore_do_suspend(hose);  in fsl_pci_syscore_suspend()
1250 static void fsl_pci_syscore_do_resume(struct pci_controller *hose)  in fsl_pci_syscore_do_resume()  argument
1252 	struct ccsr_pci __iomem *pci = hose->private_data;  in fsl_pci_syscore_do_resume()
1270 	setup_pci_atmu(hose);  in fsl_pci_syscore_do_resume()
1275 	struct pci_controller *hose, *tmp;  in fsl_pci_syscore_resume()  local
1277 	list_for_each_entry_safe(hose, tmp, &hose_list, list_node)  in fsl_pci_syscore_resume()
1278 		fsl_pci_syscore_do_resume(hose);  in fsl_pci_syscore_resume()