202 		out_be64(&priv2->mfc_control_RW, MFC_CNTL_SUSPEND_DMA_QUEUE);  in save_mfc_cntl()
285 	out_be64(&priv2->mfc_control_RW,  in halt_mfc_decr()
317 	out_be64(&prob->spc_mssync_RW, 1UL);  in do_mfc_mssync()
478 	out_be64(&priv2->mfc_control_RW,  in purge_mfc_queue()
543 	out_be64(&priv2->spu_privcntl_RW, 0UL);  in reset_spu_privcntl()
565 	out_be64(&priv2->spu_lslr_RW, LS_ADDR_MASK);  in reset_spu_lslr()
639 	out_be64(&priv2->spu_chnlcntptr_RW, 1);  in save_ch_part1()
645 		out_be64(&priv2->spu_chnlcntptr_RW, idx);  in save_ch_part1()
649 		out_be64(&priv2->spu_chnldata_RW, 0UL);  in save_ch_part1()
650 		out_be64(&priv2->spu_chnlcnt_RW, 0UL);  in save_ch_part1()
663 	out_be64(&priv2->spu_chnlcntptr_RW, 29UL);  in save_spu_mb()
669 	out_be64(&priv2->spu_chnlcnt_RW, 0UL);  in save_spu_mb()
680 	out_be64(&priv2->spu_chnlcntptr_RW, 21UL);  in save_mfc_cmd()
699 		out_be64(&priv2->spu_chnlcntptr_RW, idx);  in reset_ch()
701 		out_be64(&priv2->spu_chnlcnt_RW, ch_counts[i]);  in reset_ch()
714 	out_be64(&priv2->mfc_control_RW, MFC_CNTL_RESUME_DMA_QUEUE);  in resume_mfc_queue()
797 			out_be64(&prob->mfc_ea_W, ea);  in send_mfc_dma()
798 			out_be64(&prob->mfc_union_W.all64, command.all64);  in send_mfc_dma()
984 	out_be64(&priv2->mfc_control_RW, MFC_CNTL_SUSPEND_DMA_QUEUE |  in suspend_mfc_and_halt_decr()
1090 	out_be64(&priv2->spu_chnlcntptr_RW, 1);  in reset_ch_part1()
1091 	out_be64(&priv2->spu_chnldata_RW, 0UL);  in reset_ch_part1()
1096 		out_be64(&priv2->spu_chnlcntptr_RW, idx);  in reset_ch_part1()
1098 		out_be64(&priv2->spu_chnldata_RW, 0UL);  in reset_ch_part1()
1099 		out_be64(&priv2->spu_chnlcnt_RW, 0UL);  in reset_ch_part1()
1117 		out_be64(&priv2->spu_chnlcntptr_RW, idx);  in reset_ch_part2()
1119 		out_be64(&priv2->spu_chnlcnt_RW, ch_counts[i]);  in reset_ch_part2()
1331 	out_be64(&priv2->spu_privcntl_RW, csa->priv2.spu_privcntl_RW);  in restore_spu_privcntl()
1406 	out_be64(&priv2->mfc_control_RW, MFC_CNTL_SUSPEND_DMA_QUEUE);  in suspend_mfc()
1441 			out_be64(&priv2->puq[i].mfc_cq_data0_RW,  in restore_mfc_queues()
1443 			out_be64(&priv2->puq[i].mfc_cq_data1_RW,  in restore_mfc_queues()
1445 			out_be64(&priv2->puq[i].mfc_cq_data2_RW,  in restore_mfc_queues()
1447 			out_be64(&priv2->puq[i].mfc_cq_data3_RW,  in restore_mfc_queues()
1451 			out_be64(&priv2->spuq[i].mfc_cq_data0_RW,  in restore_mfc_queues()
1453 			out_be64(&priv2->spuq[i].mfc_cq_data1_RW,  in restore_mfc_queues()
1455 			out_be64(&priv2->spuq[i].mfc_cq_data2_RW,  in restore_mfc_queues()
1457 			out_be64(&priv2->spuq[i].mfc_cq_data3_RW,  in restore_mfc_queues()
1493 	out_be64(&priv2->spu_tag_status_query_RW,  in restore_mfc_csr_tsq()
1506 	out_be64(&priv2->spu_cmd_buf1_RW, csa->priv2.spu_cmd_buf1_RW);  in restore_mfc_csr_cmd()
1507 	out_be64(&priv2->spu_cmd_buf2_RW, csa->priv2.spu_cmd_buf2_RW);  in restore_mfc_csr_cmd()
1518 	out_be64(&priv2->spu_atomic_status_RW, csa->priv2.spu_atomic_status_RW);  in restore_mfc_csr_ato()
1582 		out_be64(&priv2->spu_chnlcntptr_RW, idx);  in restore_ch_part1()
1584 		out_be64(&priv2->spu_chnldata_RW, csa->spu_chnldata_RW[idx]);  in restore_ch_part1()
1585 		out_be64(&priv2->spu_chnlcnt_RW, csa->spu_chnlcnt_RW[idx]);  in restore_ch_part1()
1606 		out_be64(&priv2->spu_chnlcntptr_RW, idx);  in restore_ch_part2()
1608 		out_be64(&priv2->spu_chnlcnt_RW, ch_counts[i]);  in restore_ch_part2()
1620 	out_be64(&priv2->spu_lslr_RW, csa->priv2.spu_lslr_RW);  in restore_spu_lslr()
1631 	out_be64(&priv2->spu_cfg_RW, csa->priv2.spu_cfg_RW);  in restore_spu_cfg()
1662 	out_be64(&priv2->spu_chnlcntptr_RW, 29UL);  in restore_spu_mb()
1664 	out_be64(&priv2->spu_chnlcnt_RW, csa->spu_chnlcnt_RW[29]);  in restore_spu_mb()
1666 		out_be64(&priv2->spu_chnldata_RW, csa->spu_mailbox_data[i]);  in restore_spu_mb()
1748 	out_be64(&priv2->mfc_control_RW, csa->priv2.mfc_control_RW);  in restore_mfc_cntl()
1902 	out_be64(&priv2->spu_privcntl_RW, 4LL);  in force_spu_isolate_exit()
1910 	out_be64(&priv2->spu_privcntl_RW, SPU_PRIVCNT_LOAD_REQUEST_NORMAL);  in force_spu_isolate_exit()