82 void axon_msi_debug_setup(struct device_node *dn, struct axon_msic *msic);
85 					struct axon_msic *msic) { }  in axon_msi_debug_setup()  argument
89 static void msic_dcr_write(struct axon_msic *msic, unsigned int dcr_n, u32 val)  in msic_dcr_write()  argument
93 	dcr_write(msic->dcr_host, dcr_n, val);  in msic_dcr_write()
99 	struct axon_msic *msic = irq_desc_get_handler_data(desc);  in axon_msi_cascade()  local
104 	write_offset = dcr_read(msic->dcr_host, MSIC_WRITE_OFFSET_REG);  in axon_msi_cascade()
110 	while (msic->read_offset != write_offset && retry < 100) {  in axon_msi_cascade()
111 		idx  = msic->read_offset / sizeof(__le32);  in axon_msi_cascade()
112 		msi  = le32_to_cpu(msic->fifo_virt[idx]);  in axon_msi_cascade()
116 			  write_offset, msic->read_offset, msi);  in axon_msi_cascade()
118 		if (msi < nr_irqs && irq_get_chip_data(msi) == msic) {  in axon_msi_cascade()
120 			msic->fifo_virt[idx] = cpu_to_le32(0xffffffff);  in axon_msi_cascade()
140 		msic->read_offset += MSIC_FIFO_ENTRY_SIZE;  in axon_msi_cascade()
141 		msic->read_offset &= MSIC_FIFO_SIZE_MASK;  in axon_msi_cascade()
147 		msic->read_offset += MSIC_FIFO_ENTRY_SIZE;  in axon_msi_cascade()
148 		msic->read_offset &= MSIC_FIFO_SIZE_MASK;  in axon_msi_cascade()
159 	struct axon_msic *msic = NULL;  in find_msi_translator()  local
195 	msic = irq_domain->host_data;  in find_msi_translator()
200 	return msic;  in find_msi_translator()
262 	struct axon_msic *msic;  in axon_msi_setup_msi_irqs()  local
264 	msic = find_msi_translator(dev);  in axon_msi_setup_msi_irqs()
265 	if (!msic)  in axon_msi_setup_msi_irqs()
273 		virq = irq_create_direct_mapping(msic->irq_domain);  in axon_msi_setup_msi_irqs()
326 	struct axon_msic *msic = dev_get_drvdata(&device->dev);  in axon_msi_shutdown()  local
330 		 irq_domain_get_of_node(msic->irq_domain));  in axon_msi_shutdown()
331 	tmp  = dcr_read(msic->dcr_host, MSIC_CTRL_REG);  in axon_msi_shutdown()
333 	msic_dcr_write(msic, MSIC_CTRL_REG, tmp);  in axon_msi_shutdown()
339 	struct axon_msic *msic;  in axon_msi_probe()  local
345 	msic = kzalloc(sizeof(*msic), GFP_KERNEL);  in axon_msi_probe()
346 	if (!msic) {  in axon_msi_probe()
362 	msic->dcr_host = dcr_map(dn, dcr_base, dcr_len);  in axon_msi_probe()
363 	if (!DCR_MAP_OK(msic->dcr_host)) {  in axon_msi_probe()
369 	msic->fifo_virt = dma_alloc_coherent(&device->dev, MSIC_FIFO_SIZE_BYTES,  in axon_msi_probe()
370 					     &msic->fifo_phys, GFP_KERNEL);  in axon_msi_probe()
371 	if (!msic->fifo_virt) {  in axon_msi_probe()
383 	memset(msic->fifo_virt, 0xff, MSIC_FIFO_SIZE_BYTES);  in axon_msi_probe()
386 	msic->irq_domain = irq_domain_add_nomap(dn, 65536, &msic_host_ops, msic);  in axon_msi_probe()
387 	if (!msic->irq_domain) {  in axon_msi_probe()
393 	irq_set_handler_data(virq, msic);  in axon_msi_probe()
398 	msic_dcr_write(msic, MSIC_BASE_ADDR_HI_REG, msic->fifo_phys >> 32);  in axon_msi_probe()
399 	msic_dcr_write(msic, MSIC_BASE_ADDR_LO_REG,  in axon_msi_probe()
400 				  msic->fifo_phys & 0xFFFFFFFF);  in axon_msi_probe()
401 	msic_dcr_write(msic, MSIC_CTRL_REG,  in axon_msi_probe()
405 	msic->read_offset = dcr_read(msic->dcr_host, MSIC_WRITE_OFFSET_REG)  in axon_msi_probe()
408 	dev_set_drvdata(&device->dev, msic);  in axon_msi_probe()
413 	axon_msi_debug_setup(dn, msic);  in axon_msi_probe()
420 	dma_free_coherent(&device->dev, MSIC_FIFO_SIZE_BYTES, msic->fifo_virt,  in axon_msi_probe()
421 			  msic->fifo_phys);  in axon_msi_probe()
423 	kfree(msic);  in axon_msi_probe()
455 	struct axon_msic *msic = data;  in msic_set()  local
456 	out_le32(msic->trigger, val);  in msic_set()
468 void axon_msi_debug_setup(struct device_node *dn, struct axon_msic *msic)  in axon_msi_debug_setup()  argument
479 	msic->trigger = ioremap(addr, 0x4);  in axon_msi_debug_setup()
480 	if (!msic->trigger) {  in axon_msi_debug_setup()
488 				 msic, &fops_msic)) {  in axon_msi_debug_setup()