743 		mtdcri(SDR0, PESDR0_440SPE_RCSSET, 0x01010000);  in ppc440spe_pciex_check_reset()
744 		mtdcri(SDR0, PESDR1_440SPE_RCSSET, 0x01010000);  in ppc440spe_pciex_check_reset()
745 		mtdcri(SDR0, PESDR2_440SPE_RCSSET, 0x01010000);  in ppc440spe_pciex_check_reset()
857 	mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val);  in ppc440spe_pciex_init_port_hw()
858 	mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x20222222);  in ppc440spe_pciex_init_port_hw()
860 		mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x11000000);  in ppc440spe_pciex_init_port_hw()
861 	mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL0SET1, 0x35000000);  in ppc440spe_pciex_init_port_hw()
862 	mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL1SET1, 0x35000000);  in ppc440spe_pciex_init_port_hw()
863 	mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL2SET1, 0x35000000);  in ppc440spe_pciex_init_port_hw()
864 	mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL3SET1, 0x35000000);  in ppc440spe_pciex_init_port_hw()
866 		mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL4SET1,  in ppc440spe_pciex_init_port_hw()
868 		mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL5SET1,  in ppc440spe_pciex_init_port_hw()
870 		mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL6SET1,  in ppc440spe_pciex_init_port_hw()
872 		mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL7SET1,  in ppc440spe_pciex_init_port_hw()
965 	mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val);  in ppc460ex_pciex_init_port_hw()
966 	mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, utlset1);  in ppc460ex_pciex_init_port_hw()
967 	mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01210000);  in ppc460ex_pciex_init_port_hw()
971 		mtdcri(SDR0, PESDR0_460EX_L0CDRCTL, 0x00003230);  in ppc460ex_pciex_init_port_hw()
972 		mtdcri(SDR0, PESDR0_460EX_L0DRV, 0x00000130);  in ppc460ex_pciex_init_port_hw()
973 		mtdcri(SDR0, PESDR0_460EX_L0CLK, 0x00000006);  in ppc460ex_pciex_init_port_hw()
975 		mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST,0x10000000);  in ppc460ex_pciex_init_port_hw()
979 		mtdcri(SDR0, PESDR1_460EX_L0CDRCTL, 0x00003230);  in ppc460ex_pciex_init_port_hw()
980 		mtdcri(SDR0, PESDR1_460EX_L1CDRCTL, 0x00003230);  in ppc460ex_pciex_init_port_hw()
981 		mtdcri(SDR0, PESDR1_460EX_L2CDRCTL, 0x00003230);  in ppc460ex_pciex_init_port_hw()
982 		mtdcri(SDR0, PESDR1_460EX_L3CDRCTL, 0x00003230);  in ppc460ex_pciex_init_port_hw()
983 		mtdcri(SDR0, PESDR1_460EX_L0DRV, 0x00000130);  in ppc460ex_pciex_init_port_hw()
984 		mtdcri(SDR0, PESDR1_460EX_L1DRV, 0x00000130);  in ppc460ex_pciex_init_port_hw()
985 		mtdcri(SDR0, PESDR1_460EX_L2DRV, 0x00000130);  in ppc460ex_pciex_init_port_hw()
986 		mtdcri(SDR0, PESDR1_460EX_L3DRV, 0x00000130);  in ppc460ex_pciex_init_port_hw()
987 		mtdcri(SDR0, PESDR1_460EX_L0CLK, 0x00000006);  in ppc460ex_pciex_init_port_hw()
988 		mtdcri(SDR0, PESDR1_460EX_L1CLK, 0x00000006);  in ppc460ex_pciex_init_port_hw()
989 		mtdcri(SDR0, PESDR1_460EX_L2CLK, 0x00000006);  in ppc460ex_pciex_init_port_hw()
990 		mtdcri(SDR0, PESDR1_460EX_L3CLK, 0x00000006);  in ppc460ex_pciex_init_port_hw()
992 		mtdcri(SDR0, PESDR1_460EX_PHY_CTL_RST,0x10000000);  in ppc460ex_pciex_init_port_hw()
996 	mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,  in ppc460ex_pciex_init_port_hw()
1013 	mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,  in ppc460ex_pciex_init_port_hw()
1070 	mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x0);  in apm821xx_pciex_init_port_hw()
1080 	mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val);  in apm821xx_pciex_init_port_hw()
1081 	mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x00000000);  in apm821xx_pciex_init_port_hw()
1082 	mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01010000);  in apm821xx_pciex_init_port_hw()
1084 	mtdcri(SDR0, PESDR0_460EX_L0CDRCTL, 0x00003230);  in apm821xx_pciex_init_port_hw()
1085 	mtdcri(SDR0, PESDR0_460EX_L0DRV, 0x00000130);  in apm821xx_pciex_init_port_hw()
1086 	mtdcri(SDR0, PESDR0_460EX_L0CLK, 0x00000006);  in apm821xx_pciex_init_port_hw()
1088 	mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x10000000);  in apm821xx_pciex_init_port_hw()
1090 	mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x30000000);  in apm821xx_pciex_init_port_hw()
1092 	mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,  in apm821xx_pciex_init_port_hw()
1102 		mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,  in apm821xx_pciex_init_port_hw()
1123 	mtdcri(SDR0, PESDR0_460SX_HSSL0DAMP, 0xB9843211);  in ppc460sx_pciex_core_init()
1124 	mtdcri(SDR0, PESDR0_460SX_HSSL1DAMP, 0xB9843211);  in ppc460sx_pciex_core_init()
1125 	mtdcri(SDR0, PESDR0_460SX_HSSL2DAMP, 0xB9843211);  in ppc460sx_pciex_core_init()
1126 	mtdcri(SDR0, PESDR0_460SX_HSSL3DAMP, 0xB9843211);  in ppc460sx_pciex_core_init()
1127 	mtdcri(SDR0, PESDR0_460SX_HSSL4DAMP, 0xB9843211);  in ppc460sx_pciex_core_init()
1128 	mtdcri(SDR0, PESDR0_460SX_HSSL5DAMP, 0xB9843211);  in ppc460sx_pciex_core_init()
1129 	mtdcri(SDR0, PESDR0_460SX_HSSL6DAMP, 0xB9843211);  in ppc460sx_pciex_core_init()
1130 	mtdcri(SDR0, PESDR0_460SX_HSSL7DAMP, 0xB9843211);  in ppc460sx_pciex_core_init()
1132 	mtdcri(SDR0, PESDR1_460SX_HSSL0DAMP, 0xB9843211);  in ppc460sx_pciex_core_init()
1133 	mtdcri(SDR0, PESDR1_460SX_HSSL1DAMP, 0xB9843211);  in ppc460sx_pciex_core_init()
1134 	mtdcri(SDR0, PESDR1_460SX_HSSL2DAMP, 0xB9843211);  in ppc460sx_pciex_core_init()
1135 	mtdcri(SDR0, PESDR1_460SX_HSSL3DAMP, 0xB9843211);  in ppc460sx_pciex_core_init()
1137 	mtdcri(SDR0, PESDR2_460SX_HSSL0DAMP, 0xB9843211);  in ppc460sx_pciex_core_init()
1138 	mtdcri(SDR0, PESDR2_460SX_HSSL1DAMP, 0xB9843211);  in ppc460sx_pciex_core_init()
1139 	mtdcri(SDR0, PESDR2_460SX_HSSL2DAMP, 0xB9843211);  in ppc460sx_pciex_core_init()
1140 	mtdcri(SDR0, PESDR2_460SX_HSSL3DAMP, 0xB9843211);  in ppc460sx_pciex_core_init()
1143 	mtdcri(SDR0, PESDR0_460SX_HSSL0COEFA, 0xDCB98987);  in ppc460sx_pciex_core_init()
1144 	mtdcri(SDR0, PESDR0_460SX_HSSL1COEFA, 0xDCB98987);  in ppc460sx_pciex_core_init()
1145 	mtdcri(SDR0, PESDR0_460SX_HSSL2COEFA, 0xDCB98987);  in ppc460sx_pciex_core_init()
1146 	mtdcri(SDR0, PESDR0_460SX_HSSL3COEFA, 0xDCB98987);  in ppc460sx_pciex_core_init()
1147 	mtdcri(SDR0, PESDR0_460SX_HSSL4COEFA, 0xDCB98987);  in ppc460sx_pciex_core_init()
1148 	mtdcri(SDR0, PESDR0_460SX_HSSL5COEFA, 0xDCB98987);  in ppc460sx_pciex_core_init()
1149 	mtdcri(SDR0, PESDR0_460SX_HSSL6COEFA, 0xDCB98987);  in ppc460sx_pciex_core_init()
1150 	mtdcri(SDR0, PESDR0_460SX_HSSL7COEFA, 0xDCB98987);  in ppc460sx_pciex_core_init()
1152 	mtdcri(SDR0, PESDR1_460SX_HSSL0COEFA, 0xDCB98987);  in ppc460sx_pciex_core_init()
1153 	mtdcri(SDR0, PESDR1_460SX_HSSL1COEFA, 0xDCB98987);  in ppc460sx_pciex_core_init()
1154 	mtdcri(SDR0, PESDR1_460SX_HSSL2COEFA, 0xDCB98987);  in ppc460sx_pciex_core_init()
1155 	mtdcri(SDR0, PESDR1_460SX_HSSL3COEFA, 0xDCB98987);  in ppc460sx_pciex_core_init()
1157 	mtdcri(SDR0, PESDR2_460SX_HSSL0COEFA, 0xDCB98987);  in ppc460sx_pciex_core_init()
1158 	mtdcri(SDR0, PESDR2_460SX_HSSL1COEFA, 0xDCB98987);  in ppc460sx_pciex_core_init()
1159 	mtdcri(SDR0, PESDR2_460SX_HSSL2COEFA, 0xDCB98987);  in ppc460sx_pciex_core_init()
1160 	mtdcri(SDR0, PESDR2_460SX_HSSL3COEFA, 0xDCB98987);  in ppc460sx_pciex_core_init()
1163 	mtdcri(SDR0, PESDR0_460SX_HSSL1CALDRV, 0x22222222);  in ppc460sx_pciex_core_init()
1164 	mtdcri(SDR0, PESDR1_460SX_HSSL1CALDRV, 0x22220000);  in ppc460sx_pciex_core_init()
1165 	mtdcri(SDR0, PESDR2_460SX_HSSL1CALDRV, 0x22220000);  in ppc460sx_pciex_core_init()
1168 	mtdcri(SDR0, PESDR0_460SX_HSSSLEW, 0xFFFFFFFF);  in ppc460sx_pciex_core_init()
1169 	mtdcri(SDR0, PESDR1_460SX_HSSSLEW, 0xFFFF0000);  in ppc460sx_pciex_core_init()
1170 	mtdcri(SDR0, PESDR2_460SX_HSSSLEW, 0xFFFF0000);  in ppc460sx_pciex_core_init()
1173 	mtdcri(SDR0, PESDR0_460SX_HSSCTLSET, 0x00001130);  in ppc460sx_pciex_core_init()
1174 	mtdcri(SDR0, PESDR2_460SX_HSSCTLSET, 0x00001130);  in ppc460sx_pciex_core_init()
1182 	mtdcri(SDR0, PESDR0_460SX_RCSSET,  in ppc460sx_pciex_core_init()
1184 	mtdcri(SDR0, PESDR1_460SX_RCSSET,  in ppc460sx_pciex_core_init()
1186 	mtdcri(SDR0, PESDR2_460SX_RCSSET,  in ppc460sx_pciex_core_init()
1281 	mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01010000);  in ppc405ex_pcie_phy_reset()
1286 		mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01111000);  in ppc405ex_pcie_phy_reset()
1288 		mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01101000);  in ppc405ex_pcie_phy_reset()
1296 	mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x00101000);  in ppc405ex_pcie_phy_reset()
1308 	mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET,  in ppc405ex_pciex_init_port_hw()
1311 	mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x00000000);  in ppc405ex_pciex_init_port_hw()
1312 	mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01010000);  in ppc405ex_pciex_init_port_hw()
1313 	mtdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSET1, 0x720F0000);  in ppc405ex_pciex_init_port_hw()
1314 	mtdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSET2, 0x70600003);  in ppc405ex_pciex_init_port_hw()