Lines Matching refs:r3
49 addi r11,r3,THREAD_INFO_GAP
50 stwu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r3)
51 mr r1,r3
87 cmpwi cr1,r3,0
96 mullw r9,r3,r5
97 mulhwu r10,r3,r5
99 mullw r0,r3,r6
100 mulhwu r8,r3,r6
105 addze r3,r10
129 add r0,r0,r3
145 addis r4,r3,cur_cpu_spec@ha
148 add r4,r4,r3
151 add r5,r5,r3
169 cmplwi cr0,r3,0
181 rlwinm r5,r3,16,15,15 /* Clear out HID1:PS from value read */
194 cmplwi cr0,r3,0
216 insrwi r4,r3,1,9 /* insert parameter into bit 9 */
234 andc r0,r0,r3 /* And off the bits set in r3 (first parm) */
253 lbz r3,0(r3)
270 stb r3,0(r4)
288 li r3, 512
289 mtctr r3
295 lis r3, KERNELBASE@h
296 iccci 0,r3
300 mfspr r3,SPRN_L1CSR0
301 ori r3,r3,L1CSR0_CFI|L1CSR0_CLFC
303 mtspr SPRN_L1CSR0,r3
307 mfspr r3,SPRN_L1CSR1
308 ori r3,r3,L1CSR1_ICFI|L1CSR1_ICLFR
309 mtspr SPRN_L1CSR1,r3
311 mfspr r3,SPRN_PVR
312 rlwinm r3,r3,16,16,31
313 cmpwi 0,r3,1
316 mfspr r3,SPRN_HID0
317 ori r3,r3,HID0_ICFI
318 mtspr SPRN_HID0,r3
337 rlwinm r3,r3,0,0,31 - L1_CACHE_SHIFT
338 subf r4,r3,r4
343 mr r6,r3
344 1: dcbst 0,r3
345 addi r3,r3,L1_CACHE_BYTES
378 rlwinm r3,r3,0,0,31-PAGE_SHIFT /* Get page base address */
381 mr r6,r3
382 0: dcbst 0,r3 /* Write line to ram */
383 addi r3,r3,L1_CACHE_BYTES
424 rlwinm r3,r3,0,0,31-PAGE_SHIFT /* Get page base address */
427 mr r6,r3
428 0: dcbst 0,r3 /* Write line to ram */
429 addi r3,r3,L1_CACHE_BYTES
453 stw r6,4(r3); \
454 stw r7,8(r3); \
455 stw r8,12(r3); \
456 stwu r9,16(r3)
459 addi r3,r3,-4
481 dcbz r5,r3
522 slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count)
524 sraw r7,r3,r7 # t2 = MSW >> (count-32)
527 sraw r3,r3,r5 # MSW = MSW >> count
534 slw r3,r3,r5 # MSW = count > 31 ? 0 : MSW << count
538 or r3,r3,r6 # MSW |= t1
540 or r3,r3,r7 # MSW |= t2
548 slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count)
549 srw r7,r3,r7 # t2 = count < 32 ? 0 : MSW >> (count-32)
551 srw r3,r3,r5 # MSW = MSW >> count
561 cmpw r3,r5
562 li r3,1
566 1: li r3,0
568 li r3,2
576 cmplw r3,r5
577 li r3,1
581 1: li r3,0
583 li r3,2
589 rotlwi r10,r3,8
591 rlwimi r10,r3,24,0,7
593 rlwimi r10,r3,24,16,23
594 mr r3,r9
604 li r3,0
605 stw r3,0(r1) /* Zero the stack frame pointer */
628 mr r29, r3
636 mr r3, r29
644 mr r29, r3
650 mfspr r3,SPRN_PVR
651 srwi r3,r3,16
652 cmplwi cr0,r3,PVR_476FPE@h
654 cmplwi cr0,r3,PVR_476@h
656 cmplwi cr0,r3,PVR_476_ISS@h
680 li r3, 0
681 mtspr SPRN_PID, r3
685 oris r3,r3,PPC44x_MMUCR_STS@h
687 mtspr SPRN_MMUCR,r3
698 li r3,0 /* Set PAGEID inval value */
701 tlbwe r3,r4,PPC44x_TLB_PAGEID /* If not, inval the entry */
717 tlbre r3, r23, PPC44x_TLB_PAGEID
726 rlwinm r11, r3, 0, 24, 27 /* bits 24-27 */
746 insrwi r3, r7, 1, 23 /* Bit 23 is TS for PAGEID field */
749 tlbwe r3, r24, PPC44x_TLB_PAGEID
770 li r3, 0
771 tlbwe r3, r23, PPC44x_TLB_PAGEID
784 rotlwi r3, r8, 28 /* Create EPN (bits 0-3) */
785 mr r4, r3 /* RPN = EPN */
786 ori r3, r3, (PPC44x_TLB_VALID | PPC44x_TLB_256M) /* SIZE = 256M, Valid */
787 insrwi r3, r7, 1, 23 /* Set TS from r7 */
789 tlbwe r3, r6, PPC44x_TLB_PAGEID /* PageID field : EPN, V, SIZE */
816 li r3, 0
817 tlbwe r3, r24, PPC44x_TLB_PAGEID
831 li r3, 0
832 mtspr SPRN_PID, r3 /* Set PID */
836 oris r3, r3, PPC47x_MMUCR_STS@h /* Set STS=1 */
837 1: mtspr SPRN_MMUCR, r3 /* Put MMUCR */
856 addis r3, 0, 0x8000 /* specify the way */
866 tlbwe r4, r3, 0
867 tlbwe r5, r3, 1
868 tlbwe r5, r3, 2
869 addis r3, r3, 0x2000 /* Increment the way */
870 cmpwi r3, 0
872 addis r3, 0, 0x8000
888 lis r3, 0x8000 /* Way '0' */
890 tlbwe r24, r3, 0
891 tlbwe r25, r3, 1
892 tlbwe r26, r3, 2
910 li r3, 0
928 tlbwe r4, r3, 0 /* Write out the entries */
929 tlbwe r5, r3, 1
930 tlbwe r6, r3, 2
978 lis r3, 0x8000 /* Way '0' */
981 tlbwe r24, r3, 0
982 tlbwe r25, r3, 1
983 tlbwe r26, r3, 2
994 mr r3, r29
1027 mr r0, r3
1031 lwzu r0, 4(r3)
1045 rlwinm r3, r0, 0, 0, 19 /* clear kexec flags, page align */
1046 subi r3, r3, 4
1085 mfspr r3, SPRN_PIR /* current core we are running on */