Lines Matching refs:li
66 li r24,0 /* CPU number */
114 li r0,0
159 li r4, 0 /* higer 32bit */
205 li r3,0
221 li r0,0
358 li r13,_PAGE_PRESENT|_PAGE_ACCESSED
390 li r13,0
456 li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
486 li r13,0
528 li r11,PPC44x_TLB_VALID | PPC44x_TLBE_SIZE
534 li r10,0xf85 /* Mask to apply from PTE */
572 li r12,0 /* MMUCR = 0 */
595 li r13,_PAGE_PRESENT|_PAGE_ACCESSED
604 li r12,PPC47x_TLB0_VALID | PPC47x_TLBE_SIZE
606 li r12,0
669 li r12,0 /* MMUCR = 0 */
679 li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
687 li r12,PPC47x_TLB0_VALID | PPC47x_TLBE_SIZE
689 li r12,0
745 li r10,0xf85 /* Mask to apply from PTE */
783 li r3,MachineCheckA@l
870 li r4,0 /* Start at TLB entry 0 */
871 li r3,0 /* Set PAGEID inval value */
904 li r4, 0 /* Load the kernel physical address */
908 li r0,0
913 li r5,0
927 li r5,0
930 li r0,63 /* TLB slot 63 */
948 li r6,0
965 li r5,(PPC44x_TLB_SW|PPC44x_TLB_SR|PPC44x_TLB_I|PPC44x_TLB_G)
966 li r0,62 /* TLB slot 0 */
1017 li r0,0
1030 li r0,0
1071 li r5,0
1116 li r0,0
1127 li r5,0
1179 li r5,(PPC47x_TLB2_S_RW | PPC47x_TLB2_IMG)