Lines Matching refs:r10
110 mtspr SPRN_SPRG_SCRATCH0,r10; /* save two registers to work with */\
113 mfcr r10; /* save CR in r10 for now */\
122 stw r10,_CCR(r11); /* save various registers */\
125 mfspr r10,SPRN_SPRG_SCRATCH0; \
126 stw r10,GPR10(r11); \
129 mflr r10; \
130 stw r10,_LINK(r11); \
131 mfspr r10,SPRN_SPRG_SCRATCH2; \
133 stw r10,GPR1(r11); \
135 stw r10,0(r11); \
150 stw r10,crit_r10@l(0); /* save two registers to work with */\
152 mfcr r10; /* save CR in r10 for now */\
164 stw r10,_CCR(r11); /* save various registers */\
167 mflr r10; \
168 stw r10,_LINK(r11); \
218 li r10,trap; \
219 stw r10,_TRAP(r11); \
220 lis r10,msr@h; \
221 ori r10,r10,msr@l; \
222 copyee(r10, r9); \
265 mtspr SPRN_SPRG_SCRATCH0, r10 /* Save some working registers */
287 mfspr r10, SPRN_ESR
288 andis. r10, r10, ESR_DIZ@h
291 mfspr r10, SPRN_DEAR /* Get faulting address */
297 cmplw r10, r11
312 rlwimi r11, r10, 12, 20, 29 /* Create L1 (pgdir/pmd) address */
317 rlwimi r12, r10, 22, 20, 29 /* Compute PTE address */
341 tlbsx r9, 0, r10
363 mfspr r10, SPRN_SPRG_SCRATCH0
388 mfspr r10, SPRN_SPRG_SCRATCH0
454 mtspr SPRN_SPRG_SCRATCH0, r10 /* Save some working registers */
471 mfspr r10, SPRN_DEAR /* Get faulting address */
477 cmplw r10, r11
492 rlwimi r11, r10, 12, 20, 29 /* Create L1 (pgdir/pmd) address */
497 rlwimi r12, r10, 22, 20, 29 /* Compute PTE address */
509 rlwimi r10, r12, 0, 20, 31
521 rlwimi r10, r9, 0, 20, 31
546 mfspr r10, SPRN_SPRG_SCRATCH0
554 mtspr SPRN_SPRG_SCRATCH0, r10 /* Save some working registers */
571 mfspr r10, SPRN_SRR0 /* Get faulting address */
577 cmplw r10, r11
592 rlwimi r11, r10, 12, 20, 29 /* Create L1 (pgdir/pmd) address */
597 rlwimi r12, r10, 22, 20, 29 /* Compute PTE address */
609 rlwimi r10, r12, 0, 20, 31
621 rlwimi r10, r9, 0, 20, 31
646 mfspr r10, SPRN_SPRG_SCRATCH0
694 mfspr r10,SPRN_DBSR /* check single-step/branch taken */
695 andis. r10,r10,DBSR_IC@h
698 andi. r10,r9,MSR_IR|MSR_PR /* check supervisor + MMU off */
701 mfspr r10,SPRN_SRR2 /* Faulting instruction address */
702 cmplwi r10,0x2100
707 lis r10,DBSR_IC@h /* clear the IC event */
708 mtspr SPRN_DBSR,r10
710 lwz r10,_CCR(r11)
713 mtcrf 0x80,r10
718 lwz r10,crit_r10@l(0)
802 tlbwe r10, r9, TLB_TAG /* Load TLB HI */
822 mfspr r10, SPRN_SPRG_SCRATCH0