Lines Matching refs:eeh_ops

115 struct eeh_ops *eeh_ops = NULL;  variable
179 eeh_ops->read_config(pdn, PCI_VENDOR_ID, 4, &cfg); in eeh_dump_dev_log()
183 eeh_ops->read_config(pdn, PCI_COMMAND, 4, &cfg); in eeh_dump_dev_log()
189 eeh_ops->read_config(pdn, PCI_SEC_STATUS, 2, &cfg); in eeh_dump_dev_log()
193 eeh_ops->read_config(pdn, PCI_BRIDGE_CONTROL, 2, &cfg); in eeh_dump_dev_log()
201 eeh_ops->read_config(pdn, cap, 4, &cfg); in eeh_dump_dev_log()
205 eeh_ops->read_config(pdn, cap+4, 4, &cfg); in eeh_dump_dev_log()
217 eeh_ops->read_config(pdn, cap+4*i, 4, &cfg); in eeh_dump_dev_log()
244 eeh_ops->read_config(pdn, cap+4*i, 4, &cfg); in eeh_dump_dev_log()
325 eeh_ops->configure_bridge(pe); in eeh_slot_error_detail()
334 eeh_ops->get_log(pe, severity, pci_regs_buf, loglen); in eeh_slot_error_detail()
394 ret = eeh_ops->get_state(phb_pe, NULL); in eeh_phb_check_failure()
515 ret = eeh_ops->get_state(pe, NULL); in eeh_dev_check_failure()
543 ret = eeh_ops->get_state(parent_pe, NULL); in eeh_dev_check_failure()
655 rc = eeh_ops->get_state(pe, NULL); in eeh_pci_enable()
670 rc = eeh_ops->set_option(pe, function); in eeh_pci_enable()
679 rc = eeh_ops->wait_state(pe, PCI_BUS_RESET_WAIT_MSEC); in eeh_pci_enable()
730 if (pdn && eeh_ops->restore_config) in eeh_restore_dev_state()
731 eeh_ops->restore_config(pdn); in eeh_restore_dev_state()
749 eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, in eeh_restore_vf_config()
753 eeh_ops->write_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, in eeh_restore_vf_config()
757 eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCAP2, in eeh_restore_vf_config()
760 eeh_ops->read_config(pdn, in eeh_restore_vf_config()
764 eeh_ops->write_config(pdn, in eeh_restore_vf_config()
771 eeh_ops->read_config(pdn, PCI_COMMAND, 2, &cmd); in eeh_restore_vf_config()
773 eeh_ops->write_config(pdn, PCI_COMMAND, 2, cmd); in eeh_restore_vf_config()
777 eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, in eeh_restore_vf_config()
783 eeh_ops->write_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL, in eeh_restore_vf_config()
789 eeh_ops->read_config(pdn, edev->aer_cap + PCI_ERR_CAP, in eeh_restore_vf_config()
792 eeh_ops->write_config(pdn, edev->aer_cap + PCI_ERR_CAP, in eeh_restore_vf_config()
820 eeh_ops->reset(pe, EEH_RESET_DEACTIVATE); in pcibios_set_pcie_reset_state()
829 eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE); in pcibios_set_pcie_reset_state()
833 eeh_ops->reset(pe, EEH_RESET_HOT); in pcibios_set_pcie_reset_state()
837 eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE); in pcibios_set_pcie_reset_state()
841 eeh_ops->reset(pe, EEH_RESET_FUNDAMENTAL); in pcibios_set_pcie_reset_state()
916 state = eeh_ops->wait_state(pe, PCI_BUS_RESET_WAIT_MSEC); in eeh_pe_reset_full()
956 eeh_ops->read_config(pdn, i * 4, 4, &edev->config_space[i]); in eeh_save_bars()
976 int __init eeh_ops_register(struct eeh_ops *ops) in eeh_ops_register()
984 if (eeh_ops && eeh_ops != ops) { in eeh_ops_register()
986 __func__, eeh_ops->name, ops->name); in eeh_ops_register()
990 eeh_ops = ops; in eeh_ops_register()
1010 if (eeh_ops && !strcmp(eeh_ops->name, name)) { in eeh_ops_unregister()
1011 eeh_ops = NULL; in eeh_ops_unregister()
1037 traverse_pci_dn(pdn, eeh_ops->probe, NULL); in eeh_probe_devices()
1070 if (!eeh_ops) { in eeh_init()
1074 } else if ((ret = eeh_ops->init())) in eeh_init()
1126 eeh_ops->probe(pdn, NULL); in eeh_add_device_early()
1198 eeh_ops->probe(pdn, NULL); in eeh_add_device_late()
1353 ret = eeh_ops->get_state(pe, NULL); in eeh_pe_change_owner()
1548 if (!eeh_ops || !eeh_ops->set_option) { in eeh_pe_set_option()
1581 if (!eeh_ops || !eeh_ops->get_state) in eeh_pe_get_state()
1595 result = eeh_ops->get_state(pe, NULL); in eeh_pe_get_state()
1663 if (!eeh_ops || !eeh_ops->set_option || !eeh_ops->reset) in eeh_pe_reset()
1668 ret = eeh_ops->reset(pe, option); in eeh_pe_reset()
1682 eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE); in eeh_pe_reset()
1685 ret = eeh_ops->reset(pe, option); in eeh_pe_reset()
1737 if (!eeh_ops || !eeh_ops->err_inject) in eeh_pe_inject_err()
1748 return eeh_ops->err_inject(pe, type, func, addr, mask); in eeh_pe_inject_err()