452 	unsigned long newbase = R1(regs->iir)?regs->gr[R1(regs->iir)]:0;  in handle_unaligned()
481 	switch (MAJOR_OP(regs->iir))  in handle_unaligned()
486 		if (regs->iir&0x20)  in handle_unaligned()
489 			if (regs->iir&0x1000)		/* short loads */  in handle_unaligned()
490 				if (regs->iir&0x200)  in handle_unaligned()
491 					newbase += IM5_3(regs->iir);  in handle_unaligned()
493 					newbase += IM5_2(regs->iir);  in handle_unaligned()
494 			else if (regs->iir&0x2000)	/* scaled indexed */  in handle_unaligned()
497 				switch (regs->iir & OPCODE1_MASK)  in handle_unaligned()
507 				newbase += (R2(regs->iir)?regs->gr[R2(regs->iir)]:0)<<shift;  in handle_unaligned()
509 				newbase += (R2(regs->iir)?regs->gr[R2(regs->iir)]:0);  in handle_unaligned()
515 		newbase += IM14(regs->iir);  in handle_unaligned()
519 		if (regs->iir&8)  in handle_unaligned()
522 			newbase += IM14(regs->iir&~0xe);  in handle_unaligned()
528 		newbase += IM14(regs->iir&6);  in handle_unaligned()
532 		if (regs->iir&4)  in handle_unaligned()
535 			newbase += IM14(regs->iir&~4);  in handle_unaligned()
541 	switch (regs->iir & OPCODE1_MASK)  in handle_unaligned()
545 		ret = emulate_ldh(regs, R3(regs->iir));  in handle_unaligned()
552 		ret = emulate_ldw(regs, R3(regs->iir),0);  in handle_unaligned()
556 		ret = emulate_sth(regs, R2(regs->iir));  in handle_unaligned()
561 		ret = emulate_stw(regs, R2(regs->iir),0);  in handle_unaligned()
569 		ret = emulate_ldd(regs, R3(regs->iir),0);  in handle_unaligned()
574 		ret = emulate_std(regs, R2(regs->iir),0);  in handle_unaligned()
583 		ret = emulate_ldw(regs,FR3(regs->iir),1);  in handle_unaligned()
589 		ret = emulate_ldd(regs,R3(regs->iir),1);  in handle_unaligned()
597 		ret = emulate_stw(regs,FR3(regs->iir),1);  in handle_unaligned()
603 		ret = emulate_std(regs,R3(regs->iir),1);  in handle_unaligned()
614 	switch (regs->iir & OPCODE2_MASK)  in handle_unaligned()
618 		ret = emulate_ldd(regs,R2(regs->iir),1);  in handle_unaligned()
622 		ret = emulate_std(regs, R2(regs->iir),1);  in handle_unaligned()
625 		ret = emulate_ldd(regs, R2(regs->iir),0);  in handle_unaligned()
628 		ret = emulate_std(regs, R2(regs->iir),0);  in handle_unaligned()
632 	switch (regs->iir & OPCODE3_MASK)  in handle_unaligned()
636 		ret = emulate_ldw(regs, R2(regs->iir),0);  in handle_unaligned()
639 		ret = emulate_ldw(regs, R2(regs->iir),1);  in handle_unaligned()
644 		ret = emulate_stw(regs, R2(regs->iir),1);  in handle_unaligned()
647 		ret = emulate_stw(regs, R2(regs->iir),0);  in handle_unaligned()
650 	switch (regs->iir & OPCODE4_MASK)  in handle_unaligned()
653 		ret = emulate_ldh(regs, R2(regs->iir));  in handle_unaligned()
657 		ret = emulate_ldw(regs, R2(regs->iir),0);  in handle_unaligned()
660 		ret = emulate_sth(regs, R2(regs->iir));  in handle_unaligned()
664 		ret = emulate_stw(regs, R2(regs->iir),0);  in handle_unaligned()
668 	if (ret == 0 && modify && R1(regs->iir))  in handle_unaligned()
669 		regs->gr[R1(regs->iir)] = newbase;  in handle_unaligned()
673 		printk(KERN_CRIT "Not-handled unaligned insn 0x%08lx\n", regs->iir);  in handle_unaligned()
723 	switch (regs->iir & OPCODE1_MASK) {  in check_unaligned()
741 		switch (regs->iir & OPCODE4_MASK) {  in check_unaligned()