Lines Matching refs:ori
42 l.ori gpr,gpr,lo(symbol)
269 l.ori r30,r30,(EXCEPTION_SR) ;\
306 l.ori r3,r0,lo(_string_unhandled_exception) ;\
312 l.ori r3,r0,lo(_string_epc_prefix) ;\
316 l.ori r3,r0,lo(_string_nl) ;\
351 l.ori r30,r0,(EXCEPTION_SR) ;\
525 l.ori r3,r0,0x1
574 l.ori r4,r0,0x0
615 l.ori r28,r28,lo(SPR_SR_DME | SPR_SR_IME)
641 l.ori r4,r4,lo(OF_DT_HEADER)
733 l.ori r25,r25,SPR_SR_IEE
738 l.ori r25,r25,0xffff
789 l.ori r28,r28,lo(SPR_SR_DME | SPR_SR_IME)
840 l.ori r30,r0,16
849 l.ori r30,r0,1
867 l.ori r6,r6,SPR_SR_ICE
906 l.ori r30,r0,16
915 l.ori r30,r0,1
929 l.ori r6,r6,SPR_SR_DCE
1001 l.ori r5, r0, 0x1
1007 l.ori r6,r6,~(VPN_MASK) // r6 <- VPN :VPN .xfff - clear up lo(r6) to 0x**** *fff
1009 l.ori r5,r5,lo(DTLB_MR_MASK) // r5 <- ffff:1111.x001 - apply DTLB_MR_MASK
1021 l.ori r3,r3,~(PPN_MASK) // r3 <- PPN :PPN .xfff - clear up lo(r6) to 0x**** *fff
1023 l.ori r5,r5,lo(DTLB_TR_MASK) // r5 <- ffff:1111.x330 - apply DTLB_MR_MASK
1088 l.ori r5, r0, 0x1
1094 l.ori r6,r6,~(VPN_MASK) // r6 <- VPN :VPN .xfff - clear up lo(r6) to 0x**** *fff
1096 l.ori r5,r5,lo(ITLB_MR_MASK) // r5 <- ffff:1111.x001 - apply ITLB_MR_MASK
1114 l.ori r3,r3,~(PPN_MASK) // r3 <- PPN :PPN .xfff - clear up lo(r6) to 0x**** *fff
1116 l.ori r5,r5,lo(ITLB_TR_MASK) // r5 <- ffff:1111.x050 - apply ITLB_MR_MASK
1201 l.ori r3, r0, 0x1
1213 l.ori r4,r3,0x1 // set hardware valid bit: DTBL_MR entry
1286 l.ori r3, r0, 0x1
1301 l.ori r4,r4,0xc0 // | (SPR_ITLBTR_UXE | ITLBTR_SXE)
1308 l.ori r4,r3,0x1 // set hardware valid bit: ITBL_MR entry
1397 l.ori r5,r0,0x1920 // 0x1920 == l.movhi r9
1403 l.ori r5,r0,0xa929 // 0xa929 == l.ori r9
1448 l.ori r5,r0,0x1920 // 0x1920 == l.movhi r9
1454 l.ori r5,r0,0xa929 // 0xa929 == l.ori r9
1461 l.ori r5,r5,0x4400 // opcode changed from l.jalr -> l.jr
1527 l.ori r23,r0,16
1694 l.ori r4,r5,0x80
1711 l.ori r3,r0,SPR_SR_SM