Lines Matching refs:l
34 l.movhi rd,hi(-KERNELBASE) ;\
35 l.add rd,rd,rs
38 l.movhi gpr,0x0
41 l.movhi gpr,hi(symbol) ;\
42 l.ori gpr,gpr,lo(symbol)
58 #define EMERGENCY_PRINT_STORE_GPR4 l.mtspr r0,r4,SPR_SHADOW_GPR(14)
59 #define EMERGENCY_PRINT_LOAD_GPR4 l.mfspr r4,r0,SPR_SHADOW_GPR(14)
61 #define EMERGENCY_PRINT_STORE_GPR5 l.mtspr r0,r5,SPR_SHADOW_GPR(15)
62 #define EMERGENCY_PRINT_LOAD_GPR5 l.mfspr r5,r0,SPR_SHADOW_GPR(15)
64 #define EMERGENCY_PRINT_STORE_GPR6 l.mtspr r0,r6,SPR_SHADOW_GPR(16)
65 #define EMERGENCY_PRINT_LOAD_GPR6 l.mfspr r6,r0,SPR_SHADOW_GPR(16)
67 #define EMERGENCY_PRINT_STORE_GPR7 l.mtspr r0,r7,SPR_SHADOW_GPR(7)
68 #define EMERGENCY_PRINT_LOAD_GPR7 l.mfspr r7,r0,SPR_SHADOW_GPR(7)
70 #define EMERGENCY_PRINT_STORE_GPR8 l.mtspr r0,r8,SPR_SHADOW_GPR(8)
71 #define EMERGENCY_PRINT_LOAD_GPR8 l.mfspr r8,r0,SPR_SHADOW_GPR(8)
73 #define EMERGENCY_PRINT_STORE_GPR9 l.mtspr r0,r9,SPR_SHADOW_GPR(9)
74 #define EMERGENCY_PRINT_LOAD_GPR9 l.mfspr r9,r0,SPR_SHADOW_GPR(9)
77 #define EMERGENCY_PRINT_STORE_GPR4 l.sw 0x20(r0),r4
78 #define EMERGENCY_PRINT_LOAD_GPR4 l.lwz r4,0x20(r0)
80 #define EMERGENCY_PRINT_STORE_GPR5 l.sw 0x24(r0),r5
81 #define EMERGENCY_PRINT_LOAD_GPR5 l.lwz r5,0x24(r0)
83 #define EMERGENCY_PRINT_STORE_GPR6 l.sw 0x28(r0),r6
84 #define EMERGENCY_PRINT_LOAD_GPR6 l.lwz r6,0x28(r0)
86 #define EMERGENCY_PRINT_STORE_GPR7 l.sw 0x2c(r0),r7
87 #define EMERGENCY_PRINT_LOAD_GPR7 l.lwz r7,0x2c(r0)
89 #define EMERGENCY_PRINT_STORE_GPR8 l.sw 0x30(r0),r8
90 #define EMERGENCY_PRINT_LOAD_GPR8 l.lwz r8,0x30(r0)
92 #define EMERGENCY_PRINT_STORE_GPR9 l.sw 0x34(r0),r9
93 #define EMERGENCY_PRINT_LOAD_GPR9 l.lwz r9,0x34(r0)
101 #define EXCEPTION_STORE_GPR2 l.mtspr r0,r2,SPR_SHADOW_GPR(2)
102 #define EXCEPTION_LOAD_GPR2 l.mfspr r2,r0,SPR_SHADOW_GPR(2)
104 #define EXCEPTION_STORE_GPR3 l.mtspr r0,r3,SPR_SHADOW_GPR(3)
105 #define EXCEPTION_LOAD_GPR3 l.mfspr r3,r0,SPR_SHADOW_GPR(3)
107 #define EXCEPTION_STORE_GPR4 l.mtspr r0,r4,SPR_SHADOW_GPR(4)
108 #define EXCEPTION_LOAD_GPR4 l.mfspr r4,r0,SPR_SHADOW_GPR(4)
110 #define EXCEPTION_STORE_GPR5 l.mtspr r0,r5,SPR_SHADOW_GPR(5)
111 #define EXCEPTION_LOAD_GPR5 l.mfspr r5,r0,SPR_SHADOW_GPR(5)
113 #define EXCEPTION_STORE_GPR6 l.mtspr r0,r6,SPR_SHADOW_GPR(6)
114 #define EXCEPTION_LOAD_GPR6 l.mfspr r6,r0,SPR_SHADOW_GPR(6)
117 #define EXCEPTION_STORE_GPR2 l.sw 0x64(r0),r2
118 #define EXCEPTION_LOAD_GPR2 l.lwz r2,0x64(r0)
120 #define EXCEPTION_STORE_GPR3 l.sw 0x68(r0),r3
121 #define EXCEPTION_LOAD_GPR3 l.lwz r3,0x68(r0)
123 #define EXCEPTION_STORE_GPR4 l.sw 0x6c(r0),r4
124 #define EXCEPTION_LOAD_GPR4 l.lwz r4,0x6c(r0)
126 #define EXCEPTION_STORE_GPR5 l.sw 0x70(r0),r5
127 #define EXCEPTION_LOAD_GPR5 l.lwz r5,0x70(r0)
129 #define EXCEPTION_STORE_GPR6 l.sw 0x74(r0),r6
130 #define EXCEPTION_LOAD_GPR6 l.lwz r6,0x74(r0)
139 #define EXCEPTION_T_STORE_GPR30 l.mtspr r0,r30,SPR_SHADOW_GPR(30)
140 #define EXCEPTION_T_LOAD_GPR30(reg) l.mfspr reg,r0,SPR_SHADOW_GPR(30)
142 #define EXCEPTION_T_STORE_GPR10 l.mtspr r0,r10,SPR_SHADOW_GPR(10)
143 #define EXCEPTION_T_LOAD_GPR10(reg) l.mfspr reg,r0,SPR_SHADOW_GPR(10)
145 #define EXCEPTION_T_STORE_SP l.mtspr r0,r1,SPR_SHADOW_GPR(1)
146 #define EXCEPTION_T_LOAD_SP(reg) l.mfspr reg,r0,SPR_SHADOW_GPR(1)
149 #define EXCEPTION_T_STORE_GPR30 l.sw 0x78(r0),r30
150 #define EXCEPTION_T_LOAD_GPR30(reg) l.lwz reg,0x78(r0)
152 #define EXCEPTION_T_STORE_GPR10 l.sw 0x7c(r0),r10
153 #define EXCEPTION_T_LOAD_GPR10(reg) l.lwz reg,0x7c(r0)
155 #define EXCEPTION_T_STORE_SP l.sw 0x80(r0),r1
156 #define EXCEPTION_T_LOAD_SP(reg) l.lwz reg,0x80(r0)
164 l.mfspr t1,r0,SPR_COREID ;\
165 l.slli t1,t1,2 ;\
166 l.add reg,reg,t1 ;\
168 l.lwz reg,0(t1)
173 l.lwz reg,0(t1)
181 l.mfspr r10,r0,SPR_COREID ;\
182 l.slli r10,r10,2 ;\
183 l.add r30,r30,r10 ;\
185 l.lwz r10,0(r30)
191 l.lwz r10,0(r30)
227 l.mfspr r30,r0,SPR_ESR_BASE ;\
228 l.andi r30,r30,SPR_SR_SM ;\
229 l.sfeqi r30,0 ;\
231 l.bnf 2f /* kernel_mode */ ;\
236 l.lwz r1,(TI_KSP)(r30) ;\
242 l.addi r1,r1,-(INT_FRAME_SIZE) ;\
245 l.sw PT_GPR12(r30),r12 ;\
247 l.mfspr r12,r0,SPR_EPCR_BASE ;\
248 l.sw PT_PC(r30),r12 ;\
249 l.mfspr r12,r0,SPR_ESR_BASE ;\
250 l.sw PT_SR(r30),r12 ;\
253 l.sw PT_GPR30(r30),r12 ;\
256 l.sw PT_GPR10(r30),r12 ;\
259 l.sw PT_SP(r30),r12 ;\
261 l.sw PT_GPR4(r30),r4 ;\
262 l.mfspr r4,r0,SPR_EEAR_BASE ;\
267 l.mfspr r30,r0,SPR_SR ;\
268 l.andi r30,r30,SPR_SR_DSX ;\
269 l.ori r30,r30,(EXCEPTION_SR) ;\
270 l.mtspr r0,r30,SPR_ESR_BASE ;\
273 l.mtspr r0,r30,SPR_EPCR_BASE ;\
274 l.rfe
302 l.addi r1,r3,0x0 ;\
303 l.addi r10,r9,0x0 ;\
305 l.jal _emergency_print ;\
306 l.ori r3,r0,lo(_string_unhandled_exception) ;\
307 l.mfspr r3,r0,SPR_NPC ;\
308 l.jal _emergency_print_nr ;\
309 l.andi r3,r3,0x1f00 ;\
311 l.jal _emergency_print ;\
312 l.ori r3,r0,lo(_string_epc_prefix) ;\
313 l.jal _emergency_print_nr ;\
314 l.mfspr r3,r0,SPR_EPCR_BASE ;\
315 l.jal _emergency_print ;\
316 l.ori r3,r0,lo(_string_nl) ;\
318 l.addi r3,r1,0x0 ;\
319 l.addi r9,r10,0x0 ;\
326 l.addi r1,r1,-(INT_FRAME_SIZE) ;\
329 l.sw PT_GPR12(r30),r12 ;\
330 l.mfspr r12,r0,SPR_EPCR_BASE ;\
331 l.sw PT_PC(r30),r12 ;\
332 l.mfspr r12,r0,SPR_ESR_BASE ;\
333 l.sw PT_SR(r30),r12 ;\
336 l.sw PT_GPR30(r30),r12 ;\
339 l.sw PT_GPR10(r30),r12 ;\
342 l.sw PT_SP(r30),r12 ;\
343 l.sw PT_GPR13(r30),r13 ;\
346 l.sw PT_GPR4(r30),r4 ;\
347 l.mfspr r4,r0,SPR_EEAR_BASE ;\
351 l.ori r30,r0,(EXCEPTION_SR) ;\
352 l.mtspr r0,r30,SPR_ESR_BASE ;\
355 l.mtspr r0,r30,SPR_EPCR_BASE ;\
356 l.rfe
367 l.jr r13
368 l.nop
411 l.j boot_dtlb_miss_handler
412 l.nop
416 l.j boot_itlb_miss_handler
417 l.nop
519 l.or r25,r0,r3 /* pointer to fdt */
525 l.ori r3,r0,0x1
526 l.mtspr r0,r3,SPR_SR
560 l.mfspr r26,r0,SPR_COREID
561 l.sfeq r26,r0
562 l.bnf secondary_wait
563 l.nop
572 l.sw TI_KSP(r31), r1
574 l.ori r4,r0,0x0
589 l.sw (0)(r28),r0
590 l.sfltu r28,r30
591 l.bf 1b
592 l.addi r28,r28,4
595 l.jal _ic_enable
596 l.nop
599 l.jal _dc_enable
600 l.nop
603 l.jal _flush_tlb
604 l.nop
613 l.mfspr r30,r0,SPR_SR
614 l.movhi r28,hi(SPR_SR_DME | SPR_SR_IME)
615 l.ori r28,r28,lo(SPR_SR_DME | SPR_SR_IME)
616 l.or r30,r30,r28
617 l.mtspr r0,r30,SPR_SR
618 l.nop
619 l.nop
620 l.nop
621 l.nop
622 l.nop
623 l.nop
624 l.nop
625 l.nop
626 l.nop
627 l.nop
628 l.nop
629 l.nop
630 l.nop
631 l.nop
632 l.nop
633 l.nop
636 l.nop 5
639 l.lwz r3,0(r25) /* load magic from fdt into r3 */
640 l.movhi r4,hi(OF_DT_HEADER)
641 l.ori r4,r4,lo(OF_DT_HEADER)
642 l.sfeq r3,r4
643 l.bf _fdt_found
644 l.nop
646 l.or r25,r0,r0
649 l.or r3,r0,r25
651 l.jalr r24
652 l.nop
693 l.jr r30
694 l.nop
702 l.addi r7,r0,128 /* Maximum number of sets */
704 l.mtspr r5,r0,0x0
705 l.mtspr r6,r0,0x0
707 l.addi r5,r5,1
708 l.addi r6,r6,1
709 l.sfeq r7,r0
710 l.bnf 1b
711 l.addi r7,r7,-1
713 l.jr r9
714 l.nop
720 l.mfspr r25,r0,SPR_UPR
721 l.andi r25,r25,SPR_UPR_PMP
722 l.sfeq r25,r0
723 l.bf secondary_check_release
724 l.nop
729 l.mtspr r0,r25,SPR_EVBAR
732 l.mfspr r25,r0,SPR_SR
733 l.ori r25,r25,SPR_SR_IEE
734 l.mtspr r0,r25,SPR_SR
737 l.mfspr r25,r0,SPR_PICMR
738 l.ori r25,r25,0xffff
739 l.mtspr r0,r25,SPR_PICMR
742 l.mfspr r25,r0,SPR_PMR
744 l.or r25,r25,r3
745 l.mtspr r0,r25,SPR_PMR
748 l.mtspr r0,r0,SPR_EVBAR
755 l.mfspr r25,r0,SPR_COREID
758 l.lwz r3,0(r4)
759 l.sfeq r25,r3
760 l.bnf secondary_wait
761 l.nop
770 l.lwz r10,0(r30)
771 l.addi r1,r10,THREAD_SIZE
773 l.sw TI_KSP(r30),r1
775 l.jal _ic_enable
776 l.nop
778 l.jal _dc_enable
779 l.nop
781 l.jal _flush_tlb
782 l.nop
787 l.mfspr r30,r0,SPR_SR
788 l.movhi r28,hi(SPR_SR_DME | SPR_SR_IME)
789 l.ori r28,r28,lo(SPR_SR_DME | SPR_SR_IME)
790 l.or r30,r30,r28
798 l.mtspr r0,r30,SPR_ESR_BASE
800 l.mtspr r0,r30,SPR_EPCR_BASE
801 l.rfe
805 l.jr r30
806 l.nop
819 l.mfspr r24,r0,SPR_UPR
820 l.andi r26,r24,SPR_UPR_ICP
821 l.sfeq r26,r0
822 l.bf 9f
823 l.nop
826 l.mfspr r6,r0,SPR_SR
827 l.addi r5,r0,-1
828 l.xori r5,r5,SPR_SR_ICE
829 l.and r5,r6,r5
830 l.mtspr r0,r5,SPR_SR
837 l.mfspr r24,r0,SPR_ICCFGR
838 l.andi r26,r24,SPR_ICCFGR_CBS
839 l.srli r28,r26,7
840 l.ori r30,r0,16
841 l.sll r14,r30,r28
847 l.andi r26,r24,SPR_ICCFGR_NCS
848 l.srli r28,r26,3
849 l.ori r30,r0,1
850 l.sll r16,r30,r28
853 l.addi r6,r0,0
854 l.sll r5,r14,r28
859 l.mtspr r0,r6,SPR_ICBIR
860 l.sfne r6,r5
861 l.bf 1b
862 l.add r6,r6,r14
866 l.mfspr r6,r0,SPR_SR
867 l.ori r6,r6,SPR_SR_ICE
868 l.mtspr r0,r6,SPR_SR
869 l.nop
870 l.nop
871 l.nop
872 l.nop
873 l.nop
874 l.nop
875 l.nop
876 l.nop
877 l.nop
878 l.nop
880 l.jr r9
881 l.nop
885 l.mfspr r24,r0,SPR_UPR
886 l.andi r26,r24,SPR_UPR_DCP
887 l.sfeq r26,r0
888 l.bf 9f
889 l.nop
892 l.mfspr r6,r0,SPR_SR
893 l.addi r5,r0,-1
894 l.xori r5,r5,SPR_SR_DCE
895 l.and r5,r6,r5
896 l.mtspr r0,r5,SPR_SR
903 l.mfspr r24,r0,SPR_DCCFGR
904 l.andi r26,r24,SPR_DCCFGR_CBS
905 l.srli r28,r26,7
906 l.ori r30,r0,16
907 l.sll r14,r30,r28
913 l.andi r26,r24,SPR_DCCFGR_NCS
914 l.srli r28,r26,3
915 l.ori r30,r0,1
916 l.sll r16,r30,r28
919 l.addi r6,r0,0
920 l.sll r5,r14,r28
922 l.mtspr r0,r6,SPR_DCBIR
923 l.sfne r6,r5
924 l.bf 1b
925 l.add r6,r6,r14
928 l.mfspr r6,r0,SPR_SR
929 l.ori r6,r6,SPR_SR_DCE
930 l.mtspr r0,r6,SPR_SR
932 l.jr r9
933 l.nop
974 l.mfspr r6,r0,SPR_ESR_BASE //
975 l.andi r6,r6,SPR_SR_SM // are we in kernel mode ?
976 l.sfeqi r6,0 // r6 == 0x1 --> SM
977 l.bf exit_with_no_dtranslation //
978 l.nop
991 l.mfspr r4,r0,SPR_EEAR_BASE // get the offending EA
996 …l.srli r3,r4,0xd // r3 <- r4 / 8192 (sets are relative to page size (8Kb) NOT VPN…
998 l.mfspr r6, r0, SPR_DMMUCFGR
999 l.andi r6, r6, SPR_DMMUCFGR_NTS
1000 l.srli r6, r6, SPR_DMMUCFGR_NTS_OFF
1001 l.ori r5, r0, 0x1
1002 l.sll r5, r5, r6 // r5 = number DMMU sets
1003 l.addi r6, r5, -1 // r6 = nsets mask
1004 l.and r2, r3, r6 // r2 <- r3 % NSETS_MASK
1006 l.or r6,r6,r4 // r6 <- r4
1007 l.ori r6,r6,~(VPN_MASK) // r6 <- VPN :VPN .xfff - clear up lo(r6) to 0x**** *fff
1008 l.movhi r5,hi(DTLB_MR_MASK) // r5 <- ffff:0000.x000
1009 l.ori r5,r5,lo(DTLB_MR_MASK) // r5 <- ffff:1111.x001 - apply DTLB_MR_MASK
1010 l.and r5,r5,r6 // r5 <- VPN :VPN .x001 - we have DTLBMR entry
1011 l.mtspr r2,r5,SPR_DTLBMR_BASE(0) // set DTLBMR
1015 l.sfgeu r6,r4 // flag if r6 >= r4 (if 0xbfffffff >= EA)
1016 l.bf 1f // goto out
1017 l.and r3,r4,r4 // delay slot :: 24 <- r4 (if flag==1)
1021 l.ori r3,r3,~(PPN_MASK) // r3 <- PPN :PPN .xfff - clear up lo(r6) to 0x**** *fff
1022 l.movhi r5,hi(DTLB_TR_MASK) // r5 <- ffff:0000.x000
1023 l.ori r5,r5,lo(DTLB_TR_MASK) // r5 <- ffff:1111.x330 - apply DTLB_MR_MASK
1024 l.and r5,r5,r3 // r5 <- PPN :PPN .x330 - we have DTLBTR entry
1025 l.mtspr r2,r5,SPR_DTLBTR_BASE(0) // set DTLBTR
1033 l.rfe // SR <- ESR, PC <- EPC
1039 l.j _dispatch_bus_fault
1070 l.mfspr r6,r0,SPR_ESR_BASE //
1071 l.andi r6,r6,SPR_SR_SM // are we in kernel mode ?
1072 l.sfeqi r6,0 // r6 == 0x1 --> SM
1073 l.bf exit_with_no_itranslation
1074 l.nop
1078 l.mfspr r4,r0,SPR_EEAR_BASE // get the offending EA
1083 …l.srli r3,r4,0xd // r3 <- r4 / 8192 (sets are relative to page size (8Kb) NOT VP…
1085 l.mfspr r6, r0, SPR_IMMUCFGR
1086 l.andi r6, r6, SPR_IMMUCFGR_NTS
1087 l.srli r6, r6, SPR_IMMUCFGR_NTS_OFF
1088 l.ori r5, r0, 0x1
1089 l.sll r5, r5, r6 // r5 = number IMMU sets from IMMUCFGR
1090 l.addi r6, r5, -1 // r6 = nsets mask
1091 l.and r2, r3, r6 // r2 <- r3 % NSETS_MASK
1093 l.or r6,r6,r4 // r6 <- r4
1094 l.ori r6,r6,~(VPN_MASK) // r6 <- VPN :VPN .xfff - clear up lo(r6) to 0x**** *fff
1095 l.movhi r5,hi(ITLB_MR_MASK) // r5 <- ffff:0000.x000
1096 l.ori r5,r5,lo(ITLB_MR_MASK) // r5 <- ffff:1111.x001 - apply ITLB_MR_MASK
1097 l.and r5,r5,r6 // r5 <- VPN :VPN .x001 - we have ITLBMR entry
1098 l.mtspr r2,r5,SPR_ITLBMR_BASE(0) // set ITLBMR
1108 l.sfgeu r6,r4 // flag if r6 >= r4 (if 0xb0ffffff >= EA)
1109 l.bf 1f // goto out
1110 l.and r3,r4,r4 // delay slot :: 24 <- r4 (if flag==1)
1114 l.ori r3,r3,~(PPN_MASK) // r3 <- PPN :PPN .xfff - clear up lo(r6) to 0x**** *fff
1115 l.movhi r5,hi(ITLB_TR_MASK) // r5 <- ffff:0000.x000
1116 l.ori r5,r5,lo(ITLB_TR_MASK) // r5 <- ffff:1111.x050 - apply ITLB_MR_MASK
1117 l.and r5,r5,r3 // r5 <- PPN :PPN .x050 - we have ITLBTR entry
1118 l.mtspr r2,r5,SPR_ITLBTR_BASE(0) // set ITLBTR
1126 l.rfe // SR <- ESR, PC <- EPC
1131 l.j _dispatch_bus_fault
1132 l.nop
1157 l.mfspr r2,r0,SPR_EEAR_BASE
1162 l.srli r4,r2,0x18 // >> PAGE_SHIFT + (PAGE_SHIFT - 2)
1163 l.slli r4,r4,0x2 // to get address << 2
1164 l.add r3,r4,r3 // r4 is pgd_index(daddr)
1170 l.lwz r3,0x0(r4) // get *pmd value
1171 l.sfne r3,r0
1172 l.bnf d_pmd_none
1173 l.addi r3,r0,0xffffe000 // PAGE_MASK
1179 l.lwz r4,0x0(r4) // get **pmd value
1180 l.and r4,r4,r3 // & PAGE_MASK
1181 l.srli r2,r2,0xd // >> PAGE_SHIFT, r2 == EEAR
1182 l.andi r3,r2,0x7ff // (1UL << PAGE_SHIFT - 2) - 1
1183 l.slli r3,r3,0x2 // to get address << 2
1184 l.add r3,r3,r4
1185 l.lwz r3,0x0(r3) // this is pte at last
1189 l.andi r4,r3,0x1
1190 l.sfne r4,r0 // is pte present
1191 l.bnf d_pte_not_present
1192 l.addi r4,r0,0xffffe3fa // PAGE_MASK | DTLB_UP_CONVERT_MASK
1196 l.and r4,r3,r4 // apply the mask
1198 l.mfspr r2, r0, SPR_DMMUCFGR
1199 l.andi r2, r2, SPR_DMMUCFGR_NTS
1200 l.srli r2, r2, SPR_DMMUCFGR_NTS_OFF
1201 l.ori r3, r0, 0x1
1202 l.sll r3, r3, r2 // r3 = number DMMU sets DMMUCFGR
1203 l.addi r2, r3, -1 // r2 = nsets mask
1204 l.mfspr r3, r0, SPR_EEAR_BASE
1205 l.srli r3, r3, 0xd // >> PAGE_SHIFT
1206 l.and r2, r3, r2 // calc offset: & (NUM_TLB_ENTRIES-1)
1208 l.mtspr r2,r4,SPR_DTLBTR_BASE(0)
1212 l.slli r3, r3, 0xd /* << PAGE_SHIFT => EA & PAGE_MASK */
1213 l.ori r4,r3,0x1 // set hardware valid bit: DTBL_MR entry
1214 l.mtspr r2,r4,SPR_DTLBMR_BASE(0)
1219 l.rfe
1235 l.mfspr r2,r0,SPR_EEAR_BASE
1242 l.srli r4,r2,0x18 // >> PAGE_SHIFT + (PAGE_SHIFT - 2)
1243 l.slli r4,r4,0x2 // to get address << 2
1244 l.add r3,r4,r3 // r4 is pgd_index(daddr)
1250 l.lwz r3,0x0(r4) // get *pmd value
1251 l.sfne r3,r0
1252 l.bnf i_pmd_none
1253 l.addi r3,r0,0xffffe000 // PAGE_MASK
1260 l.lwz r4,0x0(r4) // get **pmd value
1261 l.and r4,r4,r3 // & PAGE_MASK
1262 l.srli r2,r2,0xd // >> PAGE_SHIFT, r2 == EEAR
1263 l.andi r3,r2,0x7ff // (1UL << PAGE_SHIFT - 2) - 1
1264 l.slli r3,r3,0x2 // to get address << 2
1265 l.add r3,r3,r4
1266 l.lwz r3,0x0(r3) // this is pte at last
1271 l.andi r4,r3,0x1
1272 l.sfne r4,r0 // is pte present
1273 l.bnf i_pte_not_present
1274 l.addi r4,r0,0xffffe03a // PAGE_MASK | ITLB_UP_CONVERT_MASK
1278 l.and r4,r3,r4 // apply the mask
1279 l.andi r3,r3,0x7c0 // _PAGE_EXEC | _PAGE_SRE | _PAGE_SWE | _PAGE_URE | _PAGE_UWE
1280 l.sfeq r3,r0
1281 l.bf itlb_tr_fill //_workaround
1283 l.mfspr r2, r0, SPR_IMMUCFGR
1284 l.andi r2, r2, SPR_IMMUCFGR_NTS
1285 l.srli r2, r2, SPR_IMMUCFGR_NTS_OFF
1286 l.ori r3, r0, 0x1
1287 l.sll r3, r3, r2 // r3 = number IMMU sets IMMUCFGR
1288 l.addi r2, r3, -1 // r2 = nsets mask
1289 l.mfspr r3, r0, SPR_EEAR_BASE
1290 l.srli r3, r3, 0xd // >> PAGE_SHIFT
1291 l.and r2, r3, r2 // calc offset: & (NUM_TLB_ENTRIES-1)
1301 l.ori r4,r4,0xc0 // | (SPR_ITLBTR_UXE | ITLBTR_SXE)
1303 l.mtspr r2,r4,SPR_ITLBTR_BASE(0)
1307 l.slli r3, r3, 0xd /* << PAGE_SHIFT => EA & PAGE_MASK */
1308 l.ori r4,r3,0x1 // set hardware valid bit: ITBL_MR entry
1309 l.mtspr r2,r4,SPR_ITLBMR_BASE(0)
1314 l.rfe
1350 l.sw TRAMP_SLOT_0(r3),r4
1351 l.sw TRAMP_SLOT_1(r3),r4
1352 l.sw TRAMP_SLOT_4(r3),r4
1353 l.sw TRAMP_SLOT_5(r3),r4
1356 l.lwz r4,0x0(r6) // load op @ EEA + 0x0 (fc address)
1357 l.sw TRAMP_SLOT_3(r3),r4 // store it to _immu_trampoline_data
1358 l.lwz r4,-0x4(r6) // load op @ EEA - 0x4 (f8 address)
1359 l.sw TRAMP_SLOT_2(r3),r4 // store it to _immu_trampoline_data
1361 l.srli r5,r4,26 // check opcode for write access
1362 l.sfeqi r5,0 // l.j
1363 l.bf 0f
1364 l.sfeqi r5,0x11 // l.jr
1365 l.bf 1f
1366 l.sfeqi r5,1 // l.jal
1367 l.bf 2f
1368 l.sfeqi r5,0x12 // l.jalr
1369 l.bf 3f
1370 l.sfeqi r5,3 // l.bnf
1371 l.bf 4f
1372 l.sfeqi r5,4 // l.bf
1373 l.bf 5f
1375 l.nop
1376 l.j 99b // should never happen
1377 l.nop 1
1394 l.addi r6,r2,0x4 // this is 0xaaaabbbb
1397 l.ori r5,r0,0x1920 // 0x1920 == l.movhi r9
1398 l.sh (TRAMP_SLOT_0+0x0)(r3),r5
1399 l.srli r5,r6,16
1400 l.sh (TRAMP_SLOT_0+0x2)(r3),r5
1403 l.ori r5,r0,0xa929 // 0xa929 == l.ori r9
1404 l.sh (TRAMP_SLOT_1+0x0)(r3),r5
1405 l.andi r5,r6,0xffff
1406 l.sh (TRAMP_SLOT_1+0x2)(r3),r5
1412 l.slli r6,r4,6 // original offset shifted left 6 - 2
1415 l.slli r4,r2,4 // old jump position: EEA shifted left 4
1418 l.addi r5,r3,0xc // new jump position (physical)
1419 l.slli r5,r5,4 // new jump position: shifted left 4
1424 l.sub r5,r4,r5 // old_jump - new_jump
1425 l.add r5,r6,r5 // orig_off + (old_jump - new_jump)
1426 l.srli r5,r5,6 // new offset shifted right 2
1430 l.sw TRAMP_SLOT_2(r3),r5 // write it back
1432 l.j trampoline_out
1433 l.nop
1445 l.addi r6,r2,0x4 // this is 0xaaaabbbb
1448 l.ori r5,r0,0x1920 // 0x1920 == l.movhi r9
1449 l.sh (TRAMP_SLOT_0+0x0)(r3),r5
1450 l.srli r5,r6,16
1451 l.sh (TRAMP_SLOT_0+0x2)(r3),r5
1454 l.ori r5,r0,0xa929 // 0xa929 == l.ori r9
1455 l.sh (TRAMP_SLOT_1+0x0)(r3),r5
1456 l.andi r5,r6,0xffff
1457 l.sh (TRAMP_SLOT_1+0x2)(r3),r5
1459 l.lhz r5,(TRAMP_SLOT_2+0x0)(r3) // load hi part of jump instruction
1460 l.andi r5,r5,0x3ff // clear out opcode part
1461 l.ori r5,r5,0x4400 // opcode changed from l.jalr -> l.jr
1462 l.sh (TRAMP_SLOT_2+0x0)(r3),r5 // write it back
1467 l.j trampoline_out
1468 l.nop
1474 l.slli r6,r4,6 // original offset shifted left 6 - 2
1477 l.slli r4,r2,4 // old jump position: EEA shifted left 4
1480 l.addi r5,r3,0xc // new jump position (physical)
1481 l.slli r5,r5,4 // new jump position: shifted left 4
1486 l.add r6,r6,r4 // (orig_off + old_jump)
1487 l.sub r6,r6,r5 // (orig_off + old_jump) - new_jump
1488 l.srli r6,r6,6 // new offset shifted right 2
1491 l.lwz r4,(TRAMP_SLOT_2+0x0)(r3) // load jump instruction
1492 l.srli r4,r4,16
1493 l.andi r4,r4,0xfc00 // get opcode part
1494 l.slli r4,r4,16
1495 l.or r6,r4,r6 // l.b(n)f new offset
1496 l.sw TRAMP_SLOT_2(r3),r6 // write it back
1500 l.addi r4,r4,(0x8 - 0x8) // jump target = r2 + 0x8 (compensate for 0x8)
1502 l.sub r4,r4,r5 // jump offset = target - new_position + 0x8
1504 l.slli r4,r4,4 // the amount of info in imediate of jump
1505 l.srli r4,r4,6 // jump instruction with offset
1506 l.sw TRAMP_SLOT_4(r3),r4 // write it to 4th slot
1513 l.mtspr r0,r5,SPR_EPCR_BASE
1524 l.mfspr r21,r0,SPR_ICCFGR
1525 l.andi r21,r21,SPR_ICCFGR_CBS
1526 l.srli r21,r21,7
1527 l.ori r23,r0,16
1528 l.sll r14,r23,r21
1530 l.mtspr r0,r5,SPR_ICBIR
1531 l.add r5,r5,r14
1532 l.mtspr r0,r5,SPR_ICBIR
1534 l.jr r9
1535 l.nop
1554 l.lbz r7,0(r3)
1555 l.sfeq r7,r0
1556 l.bf 9f
1557 l.nop
1560 l.movhi r4,hi(UART_BASE_ADD)
1562 l.addi r6,r0,0x20
1563 1: l.lbz r5,5(r4)
1564 l.andi r5,r5,0x20
1565 l.sfeq r5,r6
1566 l.bnf 1b
1567 l.nop
1569 l.sb 0(r4),r7
1571 l.addi r6,r0,0x60
1572 1: l.lbz r5,5(r4)
1573 l.andi r5,r5,0x60
1574 l.sfeq r5,r6
1575 l.bnf 1b
1576 l.nop
1579 l.j 2b
1580 l.addi r3,r3,0x1
1587 l.jr r9
1588 l.nop
1597 l.addi r8,r0,32 // shift register
1600 l.addi r8,r8,-0x4
1601 l.srl r7,r3,r8
1602 l.andi r7,r7,0xf
1605 l.sfeqi r8,0x4
1606 l.bf 2f
1607 l.nop
1609 l.sfeq r7,r0
1610 l.bf 1b
1611 l.nop
1614 l.srl r7,r3,r8
1616 l.andi r7,r7,0xf
1617 l.sflts r8,r0
1618 l.bf 9f
1620 l.sfgtui r7,0x9
1621 l.bnf 8f
1622 l.nop
1623 l.addi r7,r7,0x27
1626 l.addi r7,r7,0x30
1628 l.movhi r4,hi(UART_BASE_ADD)
1630 l.addi r6,r0,0x20
1631 1: l.lbz r5,5(r4)
1632 l.andi r5,r5,0x20
1633 l.sfeq r5,r6
1634 l.bnf 1b
1635 l.nop
1637 l.sb 0(r4),r7
1639 l.addi r6,r0,0x60
1640 1: l.lbz r5,5(r4)
1641 l.andi r5,r5,0x60
1642 l.sfeq r5,r6
1643 l.bnf 1b
1644 l.nop
1647 l.j 2b
1648 l.addi r8,r8,-0x4
1656 l.jr r9
1657 l.nop
1682 l.movhi r3,hi(UART_BASE_ADD)
1684 l.addi r4,r0,0x7
1685 l.sb 0x2(r3),r4
1687 l.addi r4,r0,0x0
1688 l.sb 0x1(r3),r4
1690 l.addi r4,r0,0x3
1691 l.sb 0x3(r3),r4
1693 l.lbz r5,3(r3)
1694 l.ori r4,r5,0x80
1695 l.sb 0x3(r3),r4
1696 l.addi r4,r0,((UART_DIVISOR>>8) & 0x000000ff)
1697 l.sb UART_DLM(r3),r4
1698 l.addi r4,r0,((UART_DIVISOR) & 0x000000ff)
1699 l.sb UART_DLL(r3),r4
1700 l.sb 0x3(r3),r5
1702 l.jr r9
1703 l.nop
1711 l.ori r3,r0,SPR_SR_SM
1712 l.mtspr r0,r3,SPR_ESR_BASE
1713 l.rfe