870 			 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);  in cop1_cfc()
880 			 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);  in cop1_cfc()
888 			 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);  in cop1_cfc()
899 			 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);  in cop1_cfc()
910 	if (MIPSInst_RT(ir))  in cop1_cfc()
911 		xcp->regs[MIPSInst_RT(ir)] = value;  in cop1_cfc()
924 	if (MIPSInst_RT(ir) == 0)  in cop1_ctc()
927 		value = xcp->regs[MIPSInst_RT(ir)];  in cop1_ctc()
932 			 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);  in cop1_ctc()
943 			 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);  in cop1_ctc()
954 			 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);  in cop1_ctc()
963 			 (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);  in cop1_ctc()
1076 		DITOREG(dval, MIPSInst_RT(ir));  in cop1Emulate()
1083 		DIFROMREG(dval, MIPSInst_RT(ir));  in cop1Emulate()
1110 		SITOREG(wval, MIPSInst_RT(ir));  in cop1Emulate()
1117 		SIFROMREG(wval, MIPSInst_RT(ir));  in cop1Emulate()
1137 			if (MIPSInst_RT(ir) != 0) {  in cop1Emulate()
1138 				DIFROMREG(xcp->regs[MIPSInst_RT(ir)],  in cop1Emulate()
1148 			DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));  in cop1Emulate()
1156 			if (MIPSInst_RT(ir) != 0) {  in cop1Emulate()
1157 				SIFROMHREG(xcp->regs[MIPSInst_RT(ir)],  in cop1Emulate()
1167 			SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));  in cop1Emulate()
1172 			if (MIPSInst_RT(ir) != 0) {  in cop1Emulate()
1173 				SIFROMREG(xcp->regs[MIPSInst_RT(ir)],  in cop1Emulate()
1180 			SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));  in cop1Emulate()
1203 			fpr = &current->thread.fpu.fpr[MIPSInst_RT(ir)];  in cop1Emulate()
1222 				cbit = fpucondbit[MIPSInst_RT(ir) >> 2];  in cop1Emulate()
1228 			switch (MIPSInst_RT(ir) & 3) {  in cop1Emulate()
1386 		cond = fpucondbit[MIPSInst_RT(ir) >> 2];  in cop1Emulate()
1387 		if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0))  in cop1Emulate()