69 		T  = 0,  enumerator
74 	#define T  macro
827 	[PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
828 	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x02, CNTR_EVEN, T },
829 	[PERF_COUNT_HW_BRANCH_MISSES] = { 0x02, CNTR_ODD, T },
836 	[PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
837 	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x27, CNTR_EVEN, T },
838 	[PERF_COUNT_HW_BRANCH_MISSES] = { 0x27, CNTR_ODD, T },
870 	[PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, T },
871 	[PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
872 	[PERF_COUNT_HW_BRANCH_MISSES] = { 0x02, CNTR_ODD, T },
897 		[C(RESULT_ACCESS)]	= { 0x0a, CNTR_EVEN, T },
898 		[C(RESULT_MISS)]	= { 0x0b, CNTR_EVEN | CNTR_ODD, T },
901 		[C(RESULT_ACCESS)]	= { 0x0a, CNTR_EVEN, T },
902 		[C(RESULT_MISS)]	= { 0x0b, CNTR_EVEN | CNTR_ODD, T },
907 		[C(RESULT_ACCESS)]	= { 0x09, CNTR_EVEN, T },
908 		[C(RESULT_MISS)]	= { 0x09, CNTR_ODD, T },
911 		[C(RESULT_ACCESS)]	= { 0x09, CNTR_EVEN, T },
912 		[C(RESULT_MISS)]	= { 0x09, CNTR_ODD, T },
915 		[C(RESULT_ACCESS)]	= { 0x14, CNTR_EVEN, T },
934 		[C(RESULT_ACCESS)]	= { 0x06, CNTR_EVEN, T },
935 		[C(RESULT_MISS)]	= { 0x06, CNTR_ODD, T },
938 		[C(RESULT_ACCESS)]	= { 0x06, CNTR_EVEN, T },
939 		[C(RESULT_MISS)]	= { 0x06, CNTR_ODD, T },
944 		[C(RESULT_ACCESS)]	= { 0x05, CNTR_EVEN, T },
945 		[C(RESULT_MISS)]	= { 0x05, CNTR_ODD, T },
948 		[C(RESULT_ACCESS)]	= { 0x05, CNTR_EVEN, T },
949 		[C(RESULT_MISS)]	= { 0x05, CNTR_ODD, T },
955 		[C(RESULT_ACCESS)]	= { 0x02, CNTR_EVEN, T },
956 		[C(RESULT_MISS)]	= { 0x02, CNTR_ODD, T },
959 		[C(RESULT_ACCESS)]	= { 0x02, CNTR_EVEN, T },
960 		[C(RESULT_MISS)]	= { 0x02, CNTR_ODD, T },
978 		[C(RESULT_ACCESS)]	= { 0x17, CNTR_ODD, T },
979 		[C(RESULT_MISS)]	= { 0x18, CNTR_ODD, T },
982 		[C(RESULT_ACCESS)]	= { 0x17, CNTR_ODD, T },
983 		[C(RESULT_MISS)]	= { 0x18, CNTR_ODD, T },
988 		[C(RESULT_ACCESS)]	= { 0x06, CNTR_EVEN, T },
989 		[C(RESULT_MISS)]	= { 0x06, CNTR_ODD, T },
992 		[C(RESULT_ACCESS)]	= { 0x06, CNTR_EVEN, T },
993 		[C(RESULT_MISS)]	= { 0x06, CNTR_ODD, T },
996 		[C(RESULT_ACCESS)]	= { 0x34, CNTR_EVEN, T },
1020 		[C(RESULT_ACCESS)]	= { 0x04, CNTR_EVEN, T },
1021 		[C(RESULT_MISS)]	= { 0x04, CNTR_ODD, T },
1024 		[C(RESULT_ACCESS)]	= { 0x04, CNTR_EVEN, T },
1025 		[C(RESULT_MISS)]	= { 0x04, CNTR_ODD, T },
1031 		[C(RESULT_ACCESS)]	= { 0x27, CNTR_EVEN, T },
1032 		[C(RESULT_MISS)]	= { 0x27, CNTR_ODD, T },
1035 		[C(RESULT_ACCESS)]	= { 0x27, CNTR_EVEN, T },
1036 		[C(RESULT_MISS)]	= { 0x27, CNTR_ODD, T },
1149 		[C(RESULT_ACCESS)]	= { 12, CNTR_EVEN, T },
1150 		[C(RESULT_MISS)]	= { 12, CNTR_ODD, T },
1153 		[C(RESULT_ACCESS)]	= { 12, CNTR_EVEN, T },
1154 		[C(RESULT_MISS)]	= { 12, CNTR_ODD, T },
1159 		[C(RESULT_ACCESS)]	= { 10, CNTR_EVEN, T },
1160 		[C(RESULT_MISS)]	= { 10, CNTR_ODD, T },
1163 		[C(RESULT_ACCESS)]	= { 10, CNTR_EVEN, T },
1164 		[C(RESULT_MISS)]	= { 10, CNTR_ODD, T },
1167 		[C(RESULT_ACCESS)]	= { 23, CNTR_EVEN, T },
1187 		[C(RESULT_MISS)]	= { 0x02, CNTR_ODD, T },
1190 		[C(RESULT_MISS)]	= { 0x02, CNTR_ODD, T },
1563 			raw_event.range = T;  in mipsxx_pmu_map_raw_event()
1619 			raw_event.range = T;  in mipsxx_pmu_map_raw_event()
1634 			raw_event.range = T;  in mipsxx_pmu_map_raw_event()