Lines Matching refs:C
83 #define C(x) PERF_COUNT_HW_CACHE_##x macro
889 [C(L1D)] = {
896 [C(OP_READ)] = {
897 [C(RESULT_ACCESS)] = { 0x0a, CNTR_EVEN, T },
898 [C(RESULT_MISS)] = { 0x0b, CNTR_EVEN | CNTR_ODD, T },
900 [C(OP_WRITE)] = {
901 [C(RESULT_ACCESS)] = { 0x0a, CNTR_EVEN, T },
902 [C(RESULT_MISS)] = { 0x0b, CNTR_EVEN | CNTR_ODD, T },
905 [C(L1I)] = {
906 [C(OP_READ)] = {
907 [C(RESULT_ACCESS)] = { 0x09, CNTR_EVEN, T },
908 [C(RESULT_MISS)] = { 0x09, CNTR_ODD, T },
910 [C(OP_WRITE)] = {
911 [C(RESULT_ACCESS)] = { 0x09, CNTR_EVEN, T },
912 [C(RESULT_MISS)] = { 0x09, CNTR_ODD, T },
914 [C(OP_PREFETCH)] = {
915 [C(RESULT_ACCESS)] = { 0x14, CNTR_EVEN, T },
922 [C(LL)] = {
923 [C(OP_READ)] = {
924 [C(RESULT_ACCESS)] = { 0x15, CNTR_ODD, P },
925 [C(RESULT_MISS)] = { 0x16, CNTR_EVEN, P },
927 [C(OP_WRITE)] = {
928 [C(RESULT_ACCESS)] = { 0x15, CNTR_ODD, P },
929 [C(RESULT_MISS)] = { 0x16, CNTR_EVEN, P },
932 [C(DTLB)] = {
933 [C(OP_READ)] = {
934 [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T },
935 [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T },
937 [C(OP_WRITE)] = {
938 [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T },
939 [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T },
942 [C(ITLB)] = {
943 [C(OP_READ)] = {
944 [C(RESULT_ACCESS)] = { 0x05, CNTR_EVEN, T },
945 [C(RESULT_MISS)] = { 0x05, CNTR_ODD, T },
947 [C(OP_WRITE)] = {
948 [C(RESULT_ACCESS)] = { 0x05, CNTR_EVEN, T },
949 [C(RESULT_MISS)] = { 0x05, CNTR_ODD, T },
952 [C(BPU)] = {
954 [C(OP_READ)] = {
955 [C(RESULT_ACCESS)] = { 0x02, CNTR_EVEN, T },
956 [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T },
958 [C(OP_WRITE)] = {
959 [C(RESULT_ACCESS)] = { 0x02, CNTR_EVEN, T },
960 [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T },
970 [C(L1D)] = {
977 [C(OP_READ)] = {
978 [C(RESULT_ACCESS)] = { 0x17, CNTR_ODD, T },
979 [C(RESULT_MISS)] = { 0x18, CNTR_ODD, T },
981 [C(OP_WRITE)] = {
982 [C(RESULT_ACCESS)] = { 0x17, CNTR_ODD, T },
983 [C(RESULT_MISS)] = { 0x18, CNTR_ODD, T },
986 [C(L1I)] = {
987 [C(OP_READ)] = {
988 [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T },
989 [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T },
991 [C(OP_WRITE)] = {
992 [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T },
993 [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T },
995 [C(OP_PREFETCH)] = {
996 [C(RESULT_ACCESS)] = { 0x34, CNTR_EVEN, T },
1003 [C(LL)] = {
1004 [C(OP_READ)] = {
1005 [C(RESULT_ACCESS)] = { 0x1c, CNTR_ODD, P },
1006 [C(RESULT_MISS)] = { 0x1d, CNTR_EVEN, P },
1008 [C(OP_WRITE)] = {
1009 [C(RESULT_ACCESS)] = { 0x1c, CNTR_ODD, P },
1010 [C(RESULT_MISS)] = { 0x1d, CNTR_EVEN, P },
1018 [C(ITLB)] = {
1019 [C(OP_READ)] = {
1020 [C(RESULT_ACCESS)] = { 0x04, CNTR_EVEN, T },
1021 [C(RESULT_MISS)] = { 0x04, CNTR_ODD, T },
1023 [C(OP_WRITE)] = {
1024 [C(RESULT_ACCESS)] = { 0x04, CNTR_EVEN, T },
1025 [C(RESULT_MISS)] = { 0x04, CNTR_ODD, T },
1028 [C(BPU)] = {
1030 [C(OP_READ)] = {
1031 [C(RESULT_ACCESS)] = { 0x27, CNTR_EVEN, T },
1032 [C(RESULT_MISS)] = { 0x27, CNTR_ODD, T },
1034 [C(OP_WRITE)] = {
1035 [C(RESULT_ACCESS)] = { 0x27, CNTR_EVEN, T },
1036 [C(RESULT_MISS)] = { 0x27, CNTR_ODD, T },
1045 [C(L1D)] = {
1046 [C(OP_READ)] = {
1047 [C(RESULT_ACCESS)] = { 0x46, CNTR_EVEN | CNTR_ODD },
1048 [C(RESULT_MISS)] = { 0x49, CNTR_EVEN | CNTR_ODD },
1050 [C(OP_WRITE)] = {
1051 [C(RESULT_ACCESS)] = { 0x47, CNTR_EVEN | CNTR_ODD },
1052 [C(RESULT_MISS)] = { 0x4a, CNTR_EVEN | CNTR_ODD },
1055 [C(L1I)] = {
1056 [C(OP_READ)] = {
1057 [C(RESULT_ACCESS)] = { 0x84, CNTR_EVEN | CNTR_ODD },
1058 [C(RESULT_MISS)] = { 0x85, CNTR_EVEN | CNTR_ODD },
1061 [C(DTLB)] = {
1063 [C(OP_READ)] = {
1064 [C(RESULT_ACCESS)] = { 0x40, CNTR_EVEN | CNTR_ODD },
1065 [C(RESULT_MISS)] = { 0x41, CNTR_EVEN | CNTR_ODD },
1067 [C(OP_WRITE)] = {
1068 [C(RESULT_ACCESS)] = { 0x40, CNTR_EVEN | CNTR_ODD },
1069 [C(RESULT_MISS)] = { 0x41, CNTR_EVEN | CNTR_ODD },
1072 [C(BPU)] = {
1074 [C(OP_READ)] = {
1075 [C(RESULT_ACCESS)] = { 0x15, CNTR_EVEN | CNTR_ODD },
1076 [C(RESULT_MISS)] = { 0x16, CNTR_EVEN | CNTR_ODD },
1085 [C(L1D)] = {
1092 [C(OP_READ)] = {
1093 [C(RESULT_MISS)] = { 0x04, CNTR_ODD },
1095 [C(OP_WRITE)] = {
1096 [C(RESULT_MISS)] = { 0x04, CNTR_ODD },
1099 [C(L1I)] = {
1100 [C(OP_READ)] = {
1101 [C(RESULT_MISS)] = { 0x04, CNTR_EVEN },
1103 [C(OP_WRITE)] = {
1104 [C(RESULT_MISS)] = { 0x04, CNTR_EVEN },
1107 [C(DTLB)] = {
1108 [C(OP_READ)] = {
1109 [C(RESULT_MISS)] = { 0x09, CNTR_ODD },
1111 [C(OP_WRITE)] = {
1112 [C(RESULT_MISS)] = { 0x09, CNTR_ODD },
1115 [C(ITLB)] = {
1116 [C(OP_READ)] = {
1117 [C(RESULT_MISS)] = { 0x0c, CNTR_ODD },
1119 [C(OP_WRITE)] = {
1120 [C(RESULT_MISS)] = { 0x0c, CNTR_ODD },
1123 [C(BPU)] = {
1125 [C(OP_READ)] = {
1126 [C(RESULT_ACCESS)] = { 0x02, CNTR_EVEN },
1127 [C(RESULT_MISS)] = { 0x02, CNTR_ODD },
1129 [C(OP_WRITE)] = {
1130 [C(RESULT_ACCESS)] = { 0x02, CNTR_EVEN },
1131 [C(RESULT_MISS)] = { 0x02, CNTR_ODD },
1141 [C(L1D)] = {
1148 [C(OP_READ)] = {
1149 [C(RESULT_ACCESS)] = { 12, CNTR_EVEN, T },
1150 [C(RESULT_MISS)] = { 12, CNTR_ODD, T },
1152 [C(OP_WRITE)] = {
1153 [C(RESULT_ACCESS)] = { 12, CNTR_EVEN, T },
1154 [C(RESULT_MISS)] = { 12, CNTR_ODD, T },
1157 [C(L1I)] = {
1158 [C(OP_READ)] = {
1159 [C(RESULT_ACCESS)] = { 10, CNTR_EVEN, T },
1160 [C(RESULT_MISS)] = { 10, CNTR_ODD, T },
1162 [C(OP_WRITE)] = {
1163 [C(RESULT_ACCESS)] = { 10, CNTR_EVEN, T },
1164 [C(RESULT_MISS)] = { 10, CNTR_ODD, T },
1166 [C(OP_PREFETCH)] = {
1167 [C(RESULT_ACCESS)] = { 23, CNTR_EVEN, T },
1174 [C(LL)] = {
1175 [C(OP_READ)] = {
1176 [C(RESULT_ACCESS)] = { 28, CNTR_EVEN, P },
1177 [C(RESULT_MISS)] = { 28, CNTR_ODD, P },
1179 [C(OP_WRITE)] = {
1180 [C(RESULT_ACCESS)] = { 28, CNTR_EVEN, P },
1181 [C(RESULT_MISS)] = { 28, CNTR_ODD, P },
1184 [C(BPU)] = {
1186 [C(OP_READ)] = {
1187 [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T },
1189 [C(OP_WRITE)] = {
1190 [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T },
1200 [C(L1D)] = {
1201 [C(OP_READ)] = {
1202 [C(RESULT_ACCESS)] = { 0x2b, CNTR_ALL },
1203 [C(RESULT_MISS)] = { 0x2e, CNTR_ALL },
1205 [C(OP_WRITE)] = {
1206 [C(RESULT_ACCESS)] = { 0x30, CNTR_ALL },
1209 [C(L1I)] = {
1210 [C(OP_READ)] = {
1211 [C(RESULT_ACCESS)] = { 0x18, CNTR_ALL },
1213 [C(OP_PREFETCH)] = {
1214 [C(RESULT_ACCESS)] = { 0x19, CNTR_ALL },
1217 [C(DTLB)] = {
1222 [C(OP_READ)] = {
1223 [C(RESULT_MISS)] = { 0x35, CNTR_ALL },
1225 [C(OP_WRITE)] = {
1226 [C(RESULT_MISS)] = { 0x35, CNTR_ALL },
1229 [C(ITLB)] = {
1230 [C(OP_READ)] = {
1231 [C(RESULT_MISS)] = { 0x37, CNTR_ALL },
1240 [C(L1D)] = {
1241 [C(OP_READ)] = {
1242 [C(RESULT_ACCESS)] = { 0x31, CNTR_ALL }, /* PAPI_L1_DCR */
1243 [C(RESULT_MISS)] = { 0x30, CNTR_ALL }, /* PAPI_L1_LDM */
1245 [C(OP_WRITE)] = {
1246 [C(RESULT_ACCESS)] = { 0x2f, CNTR_ALL }, /* PAPI_L1_DCW */
1247 [C(RESULT_MISS)] = { 0x2e, CNTR_ALL }, /* PAPI_L1_STM */
1250 [C(L1I)] = {
1251 [C(OP_READ)] = {
1252 [C(RESULT_ACCESS)] = { 0x04, CNTR_ALL }, /* PAPI_L1_ICA */
1253 [C(RESULT_MISS)] = { 0x07, CNTR_ALL }, /* PAPI_L1_ICM */
1256 [C(LL)] = {
1257 [C(OP_READ)] = {
1258 [C(RESULT_ACCESS)] = { 0x35, CNTR_ALL }, /* PAPI_L2_DCR */
1259 [C(RESULT_MISS)] = { 0x37, CNTR_ALL }, /* PAPI_L2_LDM */
1261 [C(OP_WRITE)] = {
1262 [C(RESULT_ACCESS)] = { 0x34, CNTR_ALL }, /* PAPI_L2_DCA */
1263 [C(RESULT_MISS)] = { 0x36, CNTR_ALL }, /* PAPI_L2_DCM */
1266 [C(DTLB)] = {
1271 [C(OP_READ)] = {
1272 [C(RESULT_MISS)] = { 0x2d, CNTR_ALL }, /* PAPI_TLB_DM */
1274 [C(OP_WRITE)] = {
1275 [C(RESULT_MISS)] = { 0x2d, CNTR_ALL }, /* PAPI_TLB_DM */
1278 [C(ITLB)] = {
1279 [C(OP_READ)] = {
1280 [C(RESULT_MISS)] = { 0x08, CNTR_ALL }, /* PAPI_TLB_IM */
1282 [C(OP_WRITE)] = {
1283 [C(RESULT_MISS)] = { 0x08, CNTR_ALL }, /* PAPI_TLB_IM */
1286 [C(BPU)] = {
1287 [C(OP_READ)] = {
1288 [C(RESULT_MISS)] = { 0x25, CNTR_ALL },