Lines Matching refs:MBIT_ULL
359 #define MBIT_ULL(bit) (1ULL << (bit)) macro
364 #define MIPS_CPU_TLB MBIT_ULL( 0) /* CPU has TLB */
365 #define MIPS_CPU_4KEX MBIT_ULL( 1) /* "R4K" exception model */
366 #define MIPS_CPU_3K_CACHE MBIT_ULL( 2) /* R3000-style caches */
367 #define MIPS_CPU_4K_CACHE MBIT_ULL( 3) /* R4000-style caches */
368 #define MIPS_CPU_TX39_CACHE MBIT_ULL( 4) /* TX3900-style caches */
369 #define MIPS_CPU_FPU MBIT_ULL( 5) /* CPU has FPU */
370 #define MIPS_CPU_32FPR MBIT_ULL( 6) /* 32 dbl. prec. FP registers */
371 #define MIPS_CPU_COUNTER MBIT_ULL( 7) /* Cycle count/compare */
372 #define MIPS_CPU_WATCH MBIT_ULL( 8) /* watchpoint registers */
373 #define MIPS_CPU_DIVEC MBIT_ULL( 9) /* dedicated interrupt vector */
374 #define MIPS_CPU_VCE MBIT_ULL(10) /* virt. coherence conflict possible */
375 #define MIPS_CPU_CACHE_CDEX_P MBIT_ULL(11) /* Create_Dirty_Exclusive CACHE op */
376 #define MIPS_CPU_CACHE_CDEX_S MBIT_ULL(12) /* ... same for seconary cache ... */
377 #define MIPS_CPU_MCHECK MBIT_ULL(13) /* Machine check exception */
378 #define MIPS_CPU_EJTAG MBIT_ULL(14) /* EJTAG exception */
379 #define MIPS_CPU_NOFPUEX MBIT_ULL(15) /* no FPU exception */
380 #define MIPS_CPU_LLSC MBIT_ULL(16) /* CPU has ll/sc instructions */
381 #define MIPS_CPU_INCLUSIVE_CACHES MBIT_ULL(17) /* P-cache subset enforced */
382 #define MIPS_CPU_PREFETCH MBIT_ULL(18) /* CPU has usable prefetch */
383 #define MIPS_CPU_VINT MBIT_ULL(19) /* CPU supports MIPSR2 vectored interrupts */
384 #define MIPS_CPU_VEIC MBIT_ULL(20) /* CPU supports MIPSR2 external interrupt controller mode */
385 #define MIPS_CPU_ULRI MBIT_ULL(21) /* CPU has ULRI feature */
386 #define MIPS_CPU_PCI MBIT_ULL(22) /* CPU has Perf Ctr Int indicator */
387 #define MIPS_CPU_RIXI MBIT_ULL(23) /* CPU has TLB Read/eXec Inhibit */
388 #define MIPS_CPU_MICROMIPS MBIT_ULL(24) /* CPU has microMIPS capability */
389 #define MIPS_CPU_TLBINV MBIT_ULL(25) /* CPU supports TLBINV/F */
390 #define MIPS_CPU_SEGMENTS MBIT_ULL(26) /* CPU supports Segmentation Control registers */
391 #define MIPS_CPU_EVA MBIT_ULL(27) /* CPU supports Enhanced Virtual Addressing */
392 #define MIPS_CPU_HTW MBIT_ULL(28) /* CPU support Hardware Page Table Walker */
393 #define MIPS_CPU_RIXIEX MBIT_ULL(29) /* CPU has unique exception codes for {Read, Execute}-Inhibit…
394 #define MIPS_CPU_MAAR MBIT_ULL(30) /* MAAR(I) registers are present */
395 #define MIPS_CPU_FRE MBIT_ULL(31) /* FRE & UFE bits implemented */
396 #define MIPS_CPU_RW_LLB MBIT_ULL(32) /* LLADDR/LLB writes are allowed */
397 #define MIPS_CPU_LPA MBIT_ULL(33) /* CPU supports Large Physical Addressing */
398 #define MIPS_CPU_CDMM MBIT_ULL(34) /* CPU has Common Device Memory Map */
399 #define MIPS_CPU_BP_GHIST MBIT_ULL(35) /* R12K+ Branch Prediction Global History */
400 #define MIPS_CPU_SP MBIT_ULL(36) /* Small (1KB) page support */
401 #define MIPS_CPU_FTLB MBIT_ULL(37) /* CPU has Fixed-page-size TLB */
402 #define MIPS_CPU_NAN_LEGACY MBIT_ULL(38) /* Legacy NaN implemented */
403 #define MIPS_CPU_NAN_2008 MBIT_ULL(39) /* 2008 NaN implemented */
404 #define MIPS_CPU_VP MBIT_ULL(40) /* MIPSr6 Virtual Processors (multi-threading) */
405 #define MIPS_CPU_LDPTE MBIT_ULL(41) /* CPU has ldpte/lddir instructions */
406 #define MIPS_CPU_MVH MBIT_ULL(42) /* CPU supports MFHC0/MTHC0 */
407 #define MIPS_CPU_EBASE_WG MBIT_ULL(43) /* CPU has EBase.WG */
408 #define MIPS_CPU_BADINSTR MBIT_ULL(44) /* CPU has BadInstr register */
409 #define MIPS_CPU_BADINSTRP MBIT_ULL(45) /* CPU has BadInstrP register */
410 #define MIPS_CPU_CTXTC MBIT_ULL(46) /* CPU has [X]ConfigContext registers */
411 #define MIPS_CPU_PERF MBIT_ULL(47) /* CPU has MIPS performance counters */
412 #define MIPS_CPU_GUESTCTL0EXT MBIT_ULL(48) /* CPU has VZ GuestCtl0Ext register */
413 #define MIPS_CPU_GUESTCTL1 MBIT_ULL(49) /* CPU has VZ GuestCtl1 register */
414 #define MIPS_CPU_GUESTCTL2 MBIT_ULL(50) /* CPU has VZ GuestCtl2 register */
415 #define MIPS_CPU_GUESTID MBIT_ULL(51) /* CPU uses VZ ASE GuestID feature */
416 #define MIPS_CPU_DRG MBIT_ULL(52) /* CPU has VZ Direct Root to Guest (DRG) */
417 #define MIPS_CPU_UFR MBIT_ULL(53) /* CPU supports User mode FR switching */
419 MBIT_ULL(54) /* CPU shares FTLB RAM with another */
421 MBIT_ULL(55) /* CPU shares FTLB entries with another */
423 MBIT_ULL(56) /* CPU has perf counters implemented per TC (MIPSMT ASE) */