142 	u32 ref_div;  in ar9330_clk_init()  local
152 		ref_div = 1;  in ar9330_clk_init()
167 		ref_div = t;  in ar9330_clk_init()
190 					ninit_mul, ref_div * out_div * cpu_div);  in ar9330_clk_init()
192 					ninit_mul, ref_div * out_div * ddr_div);  in ar9330_clk_init()
194 					ninit_mul, ref_div * out_div * ahb_div);  in ar9330_clk_init()
222 static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac,  in ar934x_get_pll_freq()  argument
230 	do_div(t, ref_div);  in ar934x_get_pll_freq()
235 	do_div(t, ref_div * frac);  in ar934x_get_pll_freq()
248 	u32 pll, out_div, ref_div, nint, nfrac, frac, clk_ctrl, postdiv;  in ar934x_clocks_init()  local
269 		ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) &  in ar934x_clocks_init()
276 		ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) &  in ar934x_clocks_init()
285 	cpu_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint,  in ar934x_clocks_init()
296 		ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) &  in ar934x_clocks_init()
303 		ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) &  in ar934x_clocks_init()
312 	ddr_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint,  in ar934x_clocks_init()
364 	u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;  in qca953x_clocks_init()  local
377 	ref_div = (pll >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT) &  in qca953x_clocks_init()
384 	cpu_pll = nint * ref_rate / ref_div;  in qca953x_clocks_init()
385 	cpu_pll += frac * (ref_rate >> 6) / ref_div;  in qca953x_clocks_init()
391 	ref_div = (pll >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT) &  in qca953x_clocks_init()
398 	ddr_pll = nint * ref_rate / ref_div;  in qca953x_clocks_init()
399 	ddr_pll += frac * (ref_rate >> 6) / (ref_div << 4);  in qca953x_clocks_init()
449 	u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;  in qca955x_clocks_init()  local
462 	ref_div = (pll >> QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT) &  in qca955x_clocks_init()
469 	cpu_pll = nint * ref_rate / ref_div;  in qca955x_clocks_init()
470 	cpu_pll += frac * ref_rate / (ref_div * (1 << 6));  in qca955x_clocks_init()
476 	ref_div = (pll >> QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT) &  in qca955x_clocks_init()
483 	ddr_pll = nint * ref_rate / ref_div;  in qca955x_clocks_init()
484 	ddr_pll += frac * ref_rate / (ref_div * (1 << 10));  in qca955x_clocks_init()
534 	u32 pll, out_div, ref_div, nint, hfrac, lfrac, clk_ctrl, postdiv;  in qca956x_clocks_init()  local
557 	ref_div = (pll >> QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT) &  in qca956x_clocks_init()
568 	cpu_pll = nint * ref_rate / ref_div;  in qca956x_clocks_init()
569 	cpu_pll += (lfrac * ref_rate) / ((ref_div * 25) << 13);  in qca956x_clocks_init()
570 	cpu_pll += (hfrac >> 13) * ref_rate / ref_div;  in qca956x_clocks_init()
576 	ref_div = (pll >> QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT) &  in qca956x_clocks_init()
586 	ddr_pll = nint * ref_rate / ref_div;  in qca956x_clocks_init()
587 	ddr_pll += (lfrac * ref_rate) / ((ref_div * 25) << 13);  in qca956x_clocks_init()
588 	ddr_pll += (hfrac >> 13) * ref_rate / ref_div;  in qca956x_clocks_init()