101 	.rate	= 125000000,
105 	.rate	= 150000000,
195 		base_clock = cpu_clk.rate;  in tnetd7300_get_clock()
222 	int base_clock = bus_clk.rate;  in tnetd7300_set_clock()
226 		base_clock = bus_clk.rate;  in tnetd7300_set_clock()
235 		base_clock = cpu_clk.rate;  in tnetd7300_set_clock()
257 	bus_clk.rate = tnetd7300_get_clock(BUS_PLL_SOURCE_SHIFT,  in tnetd7300_init_clocks()
261 		cpu_clk.rate = tnetd7300_get_clock(CPU_PLL_SOURCE_SHIFT,  in tnetd7300_init_clocks()
264 		cpu_clk.rate = bus_clk.rate;  in tnetd7300_init_clocks()
266 	if (dsp_clk.rate == 250000000)  in tnetd7300_init_clocks()
268 			bootcr, dsp_clk.rate);  in tnetd7300_init_clocks()
353 		bus_clk.rate =  in tnetd7200_init_clocks()
357 			bus_clk.rate);  in tnetd7200_init_clocks()
362 		cpu_clk.rate =  in tnetd7200_init_clocks()
366 			cpu_clk.rate);  in tnetd7200_init_clocks()
375 			cpu_clk.rate = ((cpu_base / cpu_prediv) * cpu_mul)  in tnetd7200_init_clocks()
379 				cpu_clk.rate);  in tnetd7200_init_clocks()
384 			bus_clk.rate = cpu_clk.rate / 2;  in tnetd7200_init_clocks()
387 				dsp_mul * 2, bus_clk.rate);  in tnetd7200_init_clocks()
394 			bus_clk.rate = ((dsp_base / dsp_prediv) * dsp_mul)  in tnetd7200_init_clocks()
398 				dsp_mul * 2, bus_clk.rate);  in tnetd7200_init_clocks()
400 			cpu_clk.rate = bus_clk.rate;  in tnetd7200_init_clocks()
404 	usb_base = bus_clk.rate;  in tnetd7200_init_clocks()
411 	dsp_clk.rate = cpu_clk.rate;  in tnetd7200_init_clocks()
436 	return clk->rate;  in clk_get_rate()
470 		dsp_clk.rate = tnetd7300_dsp_clock();  in ar7_init_clocks()
477 	vbus_clk.rate = bus_clk.rate / 2;  in ar7_init_clocks()
481 long clk_round_rate(struct clk *clk, unsigned long rate)  in clk_round_rate()  argument
488 int clk_set_rate(struct clk *clk, unsigned long rate)  in clk_set_rate()  argument