98 #define PMC_IS_LAST(i)	(pmu_conf->pmc_desc[i].type & PFM_REG_END)
99 #define PMD_IS_LAST(i)	(pmu_conf->pmd_desc[i].type & PFM_REG_END)
104 #define PMC_IS_IMPL(i)	  (i< PMU_MAX_PMCS && (pmu_conf->pmc_desc[i].type & PFM_REG_IMPL))
105 #define PMD_IS_IMPL(i)	  (i< PMU_MAX_PMDS && (pmu_conf->pmd_desc[i].type & PFM_REG_IMPL))
108 #define PMD_IS_COUNTING(i) ((pmu_conf->pmd_desc[i].type & PFM_REG_COUNTING) == PFM_REG_COUNTING)
109 #define PMC_IS_COUNTING(i) ((pmu_conf->pmc_desc[i].type & PFM_REG_COUNTING) == PFM_REG_COUNTING)
110 #define PMC_IS_MONITOR(i)  ((pmu_conf->pmc_desc[i].type & PFM_REG_MONITOR)  == PFM_REG_MONITOR)
111 #define PMC_IS_CONTROL(i)  ((pmu_conf->pmc_desc[i].type & PFM_REG_CONTROL)  == PFM_REG_CONTROL)
113 #define PMC_DFL_VAL(i)     pmu_conf->pmc_desc[i].default_value
114 #define PMC_RSVD_MASK(i)   pmu_conf->pmc_desc[i].reserved_mask
115 #define PMD_PMD_DEP(i)	   pmu_conf->pmd_desc[i].dep_pmd[0]
116 #define PMC_PMD_DEP(i)	   pmu_conf->pmc_desc[i].dep_pmd[0]
403 #define PMC_PM(cnum, val)	(((val) >> (pmu_conf->pmc_desc[cnum].pm_pos)) & 0x1)
520 static pmu_config_t		*pmu_conf;  variable
751 	return ctx->ctx_pmds[i].val + (ia64_get_pmd(i) & pmu_conf->ovfl_val);  in pfm_read_soft_counter()
760 	unsigned long ovfl_val = pmu_conf->ovfl_val;  in pfm_write_soft_counter()
931 	ovfl_mask = pmu_conf->ovfl_val;  in pfm_mask_monitoring()
1005 	ovfl_mask = pmu_conf->ovfl_val;  in pfm_restore_monitoring()
1077 		pfm_restore_ibrs(ctx->ctx_ibrs, pmu_conf->num_ibrs);  in pfm_restore_monitoring()
1078 		pfm_restore_dbrs(ctx->ctx_dbrs, pmu_conf->num_dbrs);  in pfm_restore_monitoring()
1111 	unsigned long val, ovfl_val = pmu_conf->ovfl_val;  in pfm_restore_pmds()
1127 	unsigned long ovfl_val = pmu_conf->ovfl_val;  in pfm_copy_pmds()
2509 	ctx->ctx_all_pmcs[0] = pmu_conf->impl_pmcs[0] & ~0x1;  in pfm_reset_pmu_state()
2514 	ctx->ctx_all_pmds[0] = pmu_conf->impl_pmds[0];  in pfm_reset_pmu_state()
2830 	impl_pmds = pmu_conf->impl_pmds[0];  in pfm_write_pmcs()
2863 		pmc_type   = pmu_conf->pmc_desc[cnum].type;  in pfm_write_pmcs()
2864 		pmc_pm     = (value >> pmu_conf->pmc_desc[cnum].pm_pos) & 0x1;  in pfm_write_pmcs()
2877 		wr_func = pmu_conf->pmc_desc[cnum].write_check;  in pfm_write_pmcs()
2978 		CTX_USED_PMD(ctx, pmu_conf->pmc_desc[cnum].dep_pmd[0]);  in pfm_write_pmcs()
3068 	ovfl_mask = pmu_conf->ovfl_val;  in pfm_write_pmds()
3101 		wr_func     = pmu_conf->pmd_desc[cnum].write_check;  in pfm_write_pmds()
3268 	ovfl_mask = pmu_conf->ovfl_val;  in pfm_read_pmds()
3337 		rd_func = pmu_conf->pmd_desc[cnum].read_check;  in pfm_read_pmds()
3432 	if (pmu_conf->use_rr_dbregs == 0) return 0;  in pfm_use_debug_registers()
3486 	if (pmu_conf->use_rr_dbregs == 0) return 0;  in pfm_release_debug_registers()
3687 	if (pmu_conf->use_rr_dbregs == 0) return -EINVAL;  in pfm_write_ibr_dbr()
3769 		for (i=0; i < pmu_conf->num_ibrs; i++) {  in pfm_write_ibr_dbr()
3774 		for (i=0; i < pmu_conf->num_dbrs; i++) {  in pfm_write_ibr_dbr()
4344 			pfm_restore_ibrs(ctx->ctx_ibrs, pmu_conf->num_ibrs);  in pfm_context_load()
4345 			pfm_restore_dbrs(ctx->ctx_dbrs, pmu_conf->num_dbrs);  in pfm_context_load()
4770 	if (unlikely(pmu_conf == NULL)) return -ENOSYS;  in sys_perfmonctl()
5188 	ovfl_val = pmu_conf->ovfl_val;  in pfm_overflow_handler()
5602 		pmu_conf->pmu_name,  in pfm_proc_show_header()
5605 		pmu_conf->ovfl_val,  in pfm_proc_show_header()
5606 		pmu_conf->flags);  in pfm_proc_show_header()
6001 	need_irq_resend = pmu_conf->flags & PFM_PMU_IRQ_RESEND;  in pfm_load_regs()
6028 		pfm_restore_ibrs(ctx->ctx_ibrs, pmu_conf->num_ibrs);  in pfm_load_regs()
6029 		pfm_restore_dbrs(ctx->ctx_dbrs, pmu_conf->num_dbrs);  in pfm_load_regs()
6162 		pfm_restore_ibrs(ctx->ctx_ibrs, pmu_conf->num_ibrs);  in pfm_load_regs()
6163 		pfm_restore_dbrs(ctx->ctx_dbrs, pmu_conf->num_dbrs);  in pfm_load_regs()
6170 	need_irq_resend = pmu_conf->flags & PFM_PMU_IRQ_RESEND;  in pfm_load_regs()
6306 	ovfl_val = pmu_conf->ovfl_val;  in pfm_flush_pmds()
6527 	pmu_conf = *p;  in pfm_probe_pmu()
6554 		pmu_conf->impl_pmcs[i>>6] |= 1UL << (i&63);  in pfm_init()
6557 	pmu_conf->num_pmcs = n;  in pfm_init()
6562 		pmu_conf->impl_pmds[i>>6] |= 1UL << (i&63);  in pfm_init()
6566 	pmu_conf->num_pmds      = n;  in pfm_init()
6567 	pmu_conf->num_counters  = n_counters;  in pfm_init()
6572 	if (pmu_conf->use_rr_dbregs) {  in pfm_init()
6573 		if (pmu_conf->num_ibrs > IA64_NUM_DBG_REGS) {  in pfm_init()
6574 …printk(KERN_INFO "perfmon: unsupported number of code debug registers (%u)\n", pmu_conf->num_ibrs);  in pfm_init()
6575 			pmu_conf = NULL;  in pfm_init()
6578 		if (pmu_conf->num_dbrs > IA64_NUM_DBG_REGS) {  in pfm_init()
6579 …printk(KERN_INFO "perfmon: unsupported number of data debug registers (%u)\n", pmu_conf->num_ibrs);  in pfm_init()
6580 			pmu_conf = NULL;  in pfm_init()
6586 	       pmu_conf->pmu_name,  in pfm_init()
6587 	       pmu_conf->num_pmcs,  in pfm_init()
6588 	       pmu_conf->num_pmds,  in pfm_init()
6589 	       pmu_conf->num_counters,  in pfm_init()
6590 	       ffz(pmu_conf->ovfl_val));  in pfm_init()
6593 	if (pmu_conf->num_pmds >= PFM_NUM_PMD_REGS || pmu_conf->num_pmcs >= PFM_NUM_PMC_REGS) {  in pfm_init()
6595 		pmu_conf = NULL;  in pfm_init()
6605 		pmu_conf = NULL;  in pfm_init()