Lines Matching refs:x3
52 uaccess_ttbr0_enable x2, x3, x4
57 dcache_line_size x2, x3
58 sub x3, x2, #1
59 bic x4, x0, x3
72 invalidate_icache_by_line x0, x1, x2, x3, 9f
98 uaccess_ttbr0_enable x2, x3, x4
100 invalidate_icache_by_line x0, x1, x2, x3, 2f
120 dcache_by_line_op civac, sy, x0, x1, x2, x3
138 dcache_by_line_op cvau, ish, x0, x1, x2, x3
162 dcache_line_size x2, x3
163 sub x3, x2, #1
164 tst x1, x3 // end cache line aligned?
165 bic x1, x1, x3
168 1: tst x0, x3 // start cache line aligned?
169 bic x0, x0, x3
200 dcache_by_line_op cvac, sy, x0, x1, x2, x3
215 dcache_by_line_op cvap, sy, x0, x1, x2, x3
228 dcache_by_line_op civac, sy, x0, x1, x2, x3