Lines Matching refs:x1
63 cmp x4, x1
72 invalidate_icache_by_line x0, x1, x2, x3, 9f
75 uaccess_ttbr0_disable x1, x2
100 invalidate_icache_by_line x0, x1, x2, x3, 2f
103 uaccess_ttbr0_disable x1, x2
120 dcache_by_line_op civac, sy, x0, x1, x2, x3
138 dcache_by_line_op cvau, ish, x0, x1, x2, x3
161 add x1, x1, x0
164 tst x1, x3 // end cache line aligned?
165 bic x1, x1, x3
167 dc civac, x1 // clean & invalidate D / U line
175 cmp x0, x1
200 dcache_by_line_op cvac, sy, x0, x1, x2, x3
215 dcache_by_line_op cvap, sy, x0, x1, x2, x3
228 dcache_by_line_op civac, sy, x0, x1, x2, x3