Lines Matching refs:xn
61 int xn = opcode & 0x1f; in check_cbz() local
64 (get_x_reg(regs, xn) == 0) : (get_w_reg(regs, xn) == 0); in check_cbz()
69 int xn = opcode & 0x1f; in check_cbnz() local
72 (get_x_reg(regs, xn) != 0) : (get_w_reg(regs, xn) != 0); in check_cbnz()
77 int xn = opcode & 0x1f; in check_tbz() local
80 return ((get_x_reg(regs, xn) >> bit_pos) & 0x1) == 0; in check_tbz()
85 int xn = opcode & 0x1f; in check_tbnz() local
88 return ((get_x_reg(regs, xn) >> bit_pos) & 0x1) != 0; in check_tbnz()
97 long imm, xn, val; in simulate_adr_adrp() local
99 xn = opcode & 0x1f; in simulate_adr_adrp()
107 set_x_reg(regs, xn, val); in simulate_adr_adrp()
138 int xn = (opcode >> 5) & 0x1f; in simulate_br_blr_ret() local
141 instruction_pointer_set(regs, get_x_reg(regs, xn)); in simulate_br_blr_ret()
182 int xn = opcode & 0x1f; in simulate_ldr_literal() local
189 set_x_reg(regs, xn, *load_addr); in simulate_ldr_literal()
191 set_w_reg(regs, xn, *load_addr); in simulate_ldr_literal()
200 int xn = opcode & 0x1f; in simulate_ldrsw_literal() local
206 set_x_reg(regs, xn, *load_addr); in simulate_ldrsw_literal()