Lines Matching refs:msr
411 msr sp_el0, x5 // Save thread_info
414 msr vbar_el1, x8 // vector table address
471 msr SPsel, #1 // We want to use SP_EL{1,2}
476 msr sctlr_el1, x0
482 msr sctlr_el2, x0
502 msr hcr_el2, x0
518 msr cnthctl_el2, x0
520 msr cntvoff_el2, xzr // Clear virtual offset
544 msr vpidr_el2, x0
545 msr vmpidr_el2, x1
548 msr hstr_el2, xzr // Disable CP15 traps to EL2
578 msr mdcr_el2, x3 // Configure debug traps
588 msr vttbr_el2, xzr
605 msr sctlr_el1, x0
609 msr cptr_el2, x0 // Disable copro. traps to EL2
617 msr cptr_el2, x0 // Disable copro. traps to EL2
624 msr vbar_el2, x0
629 msr spsr_el2, x0
630 msr elr_el2, lr
716 msr vbar_el1, x5
723 msr sp_el0, x2
768 msr ttbr0_el1, x3 // load TTBR0
769 msr ttbr1_el1, x4 // load TTBR1
771 msr sctlr_el1, x0
840 msr sctlr_el1, x20 // disable the MMU
847 msr sctlr_el1, x19 // re-enable the MMU