Lines Matching refs:UL
61 #define PMD_SIZE (_AC(1, UL) << PMD_SHIFT)
71 #define PUD_SIZE (_AC(1, UL) << PUD_SHIFT)
81 #define PGDIR_SIZE (_AC(1, UL) << PGDIR_SHIFT)
89 #define SECTION_SIZE (_AC(1, UL) << SECTION_SHIFT)
212 #define PHYS_MASK ((UL(1) << PHYS_MASK_SHIFT) - 1)
219 #define TCR_T0SZ(x) ((UL(64) - (x)) << TCR_T0SZ_OFFSET)
220 #define TCR_T1SZ(x) ((UL(64) - (x)) << TCR_T1SZ_OFFSET)
223 #define TCR_T0SZ_MASK (((UL(1) << TCR_TxSZ_WIDTH) - 1) << TCR_T0SZ_OFFSET)
226 #define TCR_IRGN0_MASK (UL(3) << TCR_IRGN0_SHIFT)
227 #define TCR_IRGN0_NC (UL(0) << TCR_IRGN0_SHIFT)
228 #define TCR_IRGN0_WBWA (UL(1) << TCR_IRGN0_SHIFT)
229 #define TCR_IRGN0_WT (UL(2) << TCR_IRGN0_SHIFT)
230 #define TCR_IRGN0_WBnWA (UL(3) << TCR_IRGN0_SHIFT)
233 #define TCR_IRGN1_MASK (UL(3) << TCR_IRGN1_SHIFT)
234 #define TCR_IRGN1_NC (UL(0) << TCR_IRGN1_SHIFT)
235 #define TCR_IRGN1_WBWA (UL(1) << TCR_IRGN1_SHIFT)
236 #define TCR_IRGN1_WT (UL(2) << TCR_IRGN1_SHIFT)
237 #define TCR_IRGN1_WBnWA (UL(3) << TCR_IRGN1_SHIFT)
247 #define TCR_ORGN0_MASK (UL(3) << TCR_ORGN0_SHIFT)
248 #define TCR_ORGN0_NC (UL(0) << TCR_ORGN0_SHIFT)
249 #define TCR_ORGN0_WBWA (UL(1) << TCR_ORGN0_SHIFT)
250 #define TCR_ORGN0_WT (UL(2) << TCR_ORGN0_SHIFT)
251 #define TCR_ORGN0_WBnWA (UL(3) << TCR_ORGN0_SHIFT)
254 #define TCR_ORGN1_MASK (UL(3) << TCR_ORGN1_SHIFT)
255 #define TCR_ORGN1_NC (UL(0) << TCR_ORGN1_SHIFT)
256 #define TCR_ORGN1_WBWA (UL(1) << TCR_ORGN1_SHIFT)
257 #define TCR_ORGN1_WT (UL(2) << TCR_ORGN1_SHIFT)
258 #define TCR_ORGN1_WBnWA (UL(3) << TCR_ORGN1_SHIFT)
267 #define TCR_SH0_MASK (UL(3) << TCR_SH0_SHIFT)
268 #define TCR_SH0_INNER (UL(3) << TCR_SH0_SHIFT)
271 #define TCR_SH1_MASK (UL(3) << TCR_SH1_SHIFT)
272 #define TCR_SH1_INNER (UL(3) << TCR_SH1_SHIFT)
276 #define TCR_TG0_MASK (UL(3) << TCR_TG0_SHIFT)
277 #define TCR_TG0_4K (UL(0) << TCR_TG0_SHIFT)
278 #define TCR_TG0_64K (UL(1) << TCR_TG0_SHIFT)
279 #define TCR_TG0_16K (UL(2) << TCR_TG0_SHIFT)
282 #define TCR_TG1_MASK (UL(3) << TCR_TG1_SHIFT)
283 #define TCR_TG1_16K (UL(1) << TCR_TG1_SHIFT)
284 #define TCR_TG1_4K (UL(2) << TCR_TG1_SHIFT)
285 #define TCR_TG1_64K (UL(3) << TCR_TG1_SHIFT)
288 #define TCR_IPS_MASK (UL(7) << TCR_IPS_SHIFT)
289 #define TCR_A1 (UL(1) << 22)
290 #define TCR_ASID16 (UL(1) << 36)
291 #define TCR_TBI0 (UL(1) << 37)
292 #define TCR_HA (UL(1) << 39)
293 #define TCR_HD (UL(1) << 40)
294 #define TCR_NFD1 (UL(1) << 54)
304 #define TTBR_BADDR_MASK_52 (((UL(1) << 46) - 1) << 2)