Lines Matching refs:bpmp
9 #include <dt-bindings/thermal/tegra186-bpmp-thermal.h>
54 clocks = <&bpmp TEGRA186_CLK_AXI_CBB>,
55 <&bpmp TEGRA186_CLK_EQOS_AXI>,
56 <&bpmp TEGRA186_CLK_EQOS_RX>,
57 <&bpmp TEGRA186_CLK_EQOS_TX>,
58 <&bpmp TEGRA186_CLK_EQOS_PTP_REF>;
60 resets = <&bpmp TEGRA186_RESET_EQOS>;
82 clocks = <&bpmp TEGRA186_CLK_UARTA>;
84 resets = <&bpmp TEGRA186_RESET_UARTA>;
94 clocks = <&bpmp TEGRA186_CLK_UARTB>;
96 resets = <&bpmp TEGRA186_RESET_UARTB>;
106 clocks = <&bpmp TEGRA186_CLK_UARTD>;
108 resets = <&bpmp TEGRA186_RESET_UARTD>;
118 clocks = <&bpmp TEGRA186_CLK_UARTE>;
120 resets = <&bpmp TEGRA186_RESET_UARTE>;
130 clocks = <&bpmp TEGRA186_CLK_UARTF>;
132 resets = <&bpmp TEGRA186_RESET_UARTF>;
143 clocks = <&bpmp TEGRA186_CLK_I2C1>;
145 resets = <&bpmp TEGRA186_RESET_I2C1>;
156 clocks = <&bpmp TEGRA186_CLK_I2C3>;
158 resets = <&bpmp TEGRA186_RESET_I2C3>;
170 clocks = <&bpmp TEGRA186_CLK_I2C4>;
172 resets = <&bpmp TEGRA186_RESET_I2C4>;
184 clocks = <&bpmp TEGRA186_CLK_I2C5>;
186 resets = <&bpmp TEGRA186_RESET_I2C5>;
198 clocks = <&bpmp TEGRA186_CLK_I2C6>;
200 resets = <&bpmp TEGRA186_RESET_I2C6>;
211 clocks = <&bpmp TEGRA186_CLK_I2C7>;
213 resets = <&bpmp TEGRA186_RESET_I2C7>;
224 clocks = <&bpmp TEGRA186_CLK_I2C9>;
226 resets = <&bpmp TEGRA186_RESET_I2C9>;
235 clocks = <&bpmp TEGRA186_CLK_SDMMC1>;
237 resets = <&bpmp TEGRA186_RESET_SDMMC1>;
246 clocks = <&bpmp TEGRA186_CLK_SDMMC2>;
248 resets = <&bpmp TEGRA186_RESET_SDMMC2>;
257 clocks = <&bpmp TEGRA186_CLK_SDMMC3>;
259 resets = <&bpmp TEGRA186_RESET_SDMMC3>;
268 clocks = <&bpmp TEGRA186_CLK_SDMMC4>;
270 resets = <&bpmp TEGRA186_RESET_SDMMC4>;
278 clocks = <&bpmp TEGRA186_CLK_FUSE>;
308 clocks = <&bpmp TEGRA186_CLK_I2C2>;
310 resets = <&bpmp TEGRA186_RESET_I2C2>;
321 clocks = <&bpmp TEGRA186_CLK_I2C8>;
323 resets = <&bpmp TEGRA186_RESET_I2C8>;
333 clocks = <&bpmp TEGRA186_CLK_UARTC>;
335 resets = <&bpmp TEGRA186_RESET_UARTC>;
345 clocks = <&bpmp TEGRA186_CLK_UARTG>;
347 resets = <&bpmp TEGRA186_RESET_UARTG>;
377 nvidia,bpmp = <&bpmp>;
382 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>;
408 clocks = <&bpmp TEGRA186_CLK_AFI>,
409 <&bpmp TEGRA186_CLK_PCIE>,
410 <&bpmp TEGRA186_CLK_PLLE>;
413 resets = <&bpmp TEGRA186_RESET_AFI>,
414 <&bpmp TEGRA186_RESET_PCIE>,
415 <&bpmp TEGRA186_RESET_PCIEXCLK>;
540 clocks = <&bpmp TEGRA186_CLK_HOST1X>;
542 resets = <&bpmp TEGRA186_RESET_HOST1X>;
555 clocks = <&bpmp TEGRA186_CLK_DPAUX1>,
556 <&bpmp TEGRA186_CLK_PLLDP>;
558 resets = <&bpmp TEGRA186_RESET_DPAUX1>;
562 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
587 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>,
588 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>,
589 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>,
590 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>,
591 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>,
592 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>,
593 <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>;
596 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>,
597 <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>,
598 <&bpmp TEGRA186_CLK_NVDISPLAYHUB>;
602 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
613 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>;
615 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>;
618 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
629 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>;
631 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>;
634 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>;
645 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>;
647 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>;
650 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>;
662 clocks = <&bpmp TEGRA186_CLK_DSI>,
663 <&bpmp TEGRA186_CLK_DSIA_LP>,
664 <&bpmp TEGRA186_CLK_PLLD>;
666 resets = <&bpmp TEGRA186_RESET_DSI>;
670 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
677 clocks = <&bpmp TEGRA186_CLK_VIC>;
679 resets = <&bpmp TEGRA186_RESET_VIC>;
682 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>;
689 clocks = <&bpmp TEGRA186_CLK_DSIB>,
690 <&bpmp TEGRA186_CLK_DSIB_LP>,
691 <&bpmp TEGRA186_CLK_PLLD>;
693 resets = <&bpmp TEGRA186_RESET_DSIB>;
697 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
704 clocks = <&bpmp TEGRA186_CLK_SOR0>,
705 <&bpmp TEGRA186_CLK_SOR0_OUT>,
706 <&bpmp TEGRA186_CLK_PLLD2>,
707 <&bpmp TEGRA186_CLK_PLLDP>,
708 <&bpmp TEGRA186_CLK_SOR_SAFE>,
709 <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>;
712 resets = <&bpmp TEGRA186_RESET_SOR0>;
720 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
728 clocks = <&bpmp TEGRA186_CLK_SOR1>,
729 <&bpmp TEGRA186_CLK_SOR1_OUT>,
730 <&bpmp TEGRA186_CLK_PLLD3>,
731 <&bpmp TEGRA186_CLK_PLLDP>,
732 <&bpmp TEGRA186_CLK_SOR_SAFE>,
733 <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>;
736 resets = <&bpmp TEGRA186_RESET_SOR1>;
744 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
752 clocks = <&bpmp TEGRA186_CLK_DPAUX>,
753 <&bpmp TEGRA186_CLK_PLLDP>;
755 resets = <&bpmp TEGRA186_RESET_DPAUX>;
759 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
785 resets = <&bpmp TEGRA186_RESET_DSI>;
794 clocks = <&bpmp TEGRA186_CLK_DSIC>,
795 <&bpmp TEGRA186_CLK_DSIC_LP>,
796 <&bpmp TEGRA186_CLK_PLLD>;
798 resets = <&bpmp TEGRA186_RESET_DSIC>;
802 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
809 clocks = <&bpmp TEGRA186_CLK_DSID>,
810 <&bpmp TEGRA186_CLK_DSID_LP>,
811 <&bpmp TEGRA186_CLK_PLLD>;
813 resets = <&bpmp TEGRA186_RESET_DSID>;
817 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
829 clocks = <&bpmp TEGRA186_CLK_GPCCLK>,
830 <&bpmp TEGRA186_CLK_GPU>;
832 resets = <&bpmp TEGRA186_RESET_GPU>;
836 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>;
847 compatible = "nvidia,tegra186-bpmp-shmem";
849 label = "cpu-bpmp-tx";
854 compatible = "nvidia,tegra186-bpmp-shmem";
856 label = "cpu-bpmp-rx";
902 bpmp: bpmp { label
903 compatible = "nvidia,tegra186-bpmp";
912 compatible = "nvidia,tegra186-bpmp-i2c";
913 nvidia,bpmp-bus-id = <5>;
920 compatible = "nvidia,tegra186-bpmp-thermal";