Lines Matching refs:pericfg
213 pericfg: pericfg@10002000 { label
214 compatible = "mediatek,mt7622-pericfg",
331 clocks = <&pericfg CLK_PERI_AUXADC_PD>;
342 <&pericfg CLK_PERI_UART0_PD>;
353 <&pericfg CLK_PERI_UART1_PD>;
364 <&pericfg CLK_PERI_UART2_PD>;
375 <&pericfg CLK_PERI_UART3_PD>;
385 <&pericfg CLK_PERI_PWM_PD>,
386 <&pericfg CLK_PERI_PWM1_PD>,
387 <&pericfg CLK_PERI_PWM2_PD>,
388 <&pericfg CLK_PERI_PWM3_PD>,
389 <&pericfg CLK_PERI_PWM4_PD>,
390 <&pericfg CLK_PERI_PWM5_PD>,
391 <&pericfg CLK_PERI_PWM6_PD>;
403 clocks = <&pericfg CLK_PERI_I2C0_PD>,
404 <&pericfg CLK_PERI_AP_DMA_PD>;
417 clocks = <&pericfg CLK_PERI_I2C1_PD>,
418 <&pericfg CLK_PERI_AP_DMA_PD>;
431 clocks = <&pericfg CLK_PERI_I2C2_PD>,
432 <&pericfg CLK_PERI_AP_DMA_PD>;
445 <&pericfg CLK_PERI_SPI0_PD>;
457 clocks = <&pericfg CLK_PERI_THERM_PD>,
458 <&pericfg CLK_PERI_AUXADC_PD>;
460 resets = <&pericfg MT7622_PERI_THERM_SW_RST>;
473 clocks = <&pericfg CLK_PERI_BTIF_PD>;
484 clocks = <&pericfg CLK_PERI_NFI_PD>,
485 <&pericfg CLK_PERI_SNFI_PD>;
497 clocks = <&pericfg CLK_PERI_NFIECC_PD>;
506 clocks = <&pericfg CLK_PERI_FLASH_PD>,
520 <&pericfg CLK_PERI_SPI1_PD>;
533 <&pericfg CLK_PERI_UART4_PD>;
631 clocks = <&pericfg CLK_PERI_MSDC30_0_PD>,
641 clocks = <&pericfg CLK_PERI_MSDC30_1_PD>,