Lines Matching refs:PWRSTS_OFF_RET
41 [0] = PWRSTS_OFF_RET, /* core_nret_bank */
42 [1] = PWRSTS_OFF_RET, /* core_ocmram */
43 [2] = PWRSTS_OFF_RET, /* core_other_bank */
44 [3] = PWRSTS_OFF_RET, /* ipu_l2ram */
45 [4] = PWRSTS_OFF_RET, /* ipu_unicache */
48 [0] = PWRSTS_OFF_RET, /* core_nret_bank */
49 [1] = PWRSTS_OFF_RET, /* core_ocmram */
50 [2] = PWRSTS_OFF_RET, /* core_other_bank */
51 [3] = PWRSTS_OFF_RET, /* ipu_l2ram */
52 [4] = PWRSTS_OFF_RET, /* ipu_unicache */
67 [0] = PWRSTS_OFF_RET, /* aessmem */
68 [1] = PWRSTS_OFF_RET, /* periphmem */
71 [0] = PWRSTS_OFF_RET, /* aessmem */
72 [1] = PWRSTS_OFF_RET, /* periphmem */
96 [0] = PWRSTS_OFF_RET, /* dss_mem */
99 [0] = PWRSTS_OFF_RET, /* dss_mem */
114 [0] = PWRSTS_OFF_RET, /* cpu0_l1 */
131 [0] = PWRSTS_OFF_RET, /* cpu1_l1 */
147 [0] = PWRSTS_OFF_RET, /* emu_bank */
150 [0] = PWRSTS_OFF_RET, /* emu_bank */
164 [0] = PWRSTS_OFF_RET, /* mpu_l2 */
168 [0] = PWRSTS_OFF_RET, /* mpu_l2 */
169 [1] = PWRSTS_OFF_RET, /* mpu_ram */
190 .pwrsts_logic_ret = PWRSTS_OFF_RET,
193 [0] = PWRSTS_OFF_RET, /* dsp_edma */
194 [1] = PWRSTS_OFF_RET, /* dsp_l1 */
195 [2] = PWRSTS_OFF_RET, /* dsp_l2 */
198 [0] = PWRSTS_OFF_RET, /* dsp_edma */
199 [1] = PWRSTS_OFF_RET, /* dsp_l1 */
200 [2] = PWRSTS_OFF_RET, /* dsp_l2 */
214 [0] = PWRSTS_OFF_RET, /* cam_mem */
217 [0] = PWRSTS_OFF_RET, /* cam_mem */
229 .pwrsts_logic_ret = PWRSTS_OFF_RET,
232 [0] = PWRSTS_OFF_RET, /* l3init_bank1 */
233 [1] = PWRSTS_OFF_RET, /* l3init_bank2 */
236 [0] = PWRSTS_OFF_RET, /* l3init_bank1 */
237 [1] = PWRSTS_OFF_RET, /* l3init_bank2 */
251 [0] = PWRSTS_OFF_RET, /* gpu_mem */
254 [0] = PWRSTS_OFF_RET, /* gpu_mem */
284 [0] = PWRSTS_OFF_RET, /* hwa_mem */
285 [1] = PWRSTS_OFF_RET, /* sl2_mem */
286 [2] = PWRSTS_OFF_RET, /* tcm1_mem */
287 [3] = PWRSTS_OFF_RET, /* tcm2_mem */
290 [0] = PWRSTS_OFF_RET, /* hwa_mem */
291 [1] = PWRSTS_OFF_RET, /* sl2_mem */
292 [2] = PWRSTS_OFF_RET, /* tcm1_mem */
293 [3] = PWRSTS_OFF_RET, /* tcm2_mem */