Lines Matching refs:context_offs
63 .context_offs = DRA7XX_RM_EMIF_DMM_CONTEXT_OFFSET,
84 .context_offs = DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
98 .context_offs = DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
111 .context_offs = DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET,
133 .context_offs = DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
185 .context_offs = DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
208 .context_offs = DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET,
232 .context_offs = DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET,
267 .context_offs = DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
323 .context_offs = DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET,
362 .context_offs = DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET,
378 .context_offs = DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET,
411 .context_offs = DRA7XX_RM_L4PER2_PWMSS1_CONTEXT_OFFSET,
426 .context_offs = DRA7XX_RM_L4PER2_PWMSS2_CONTEXT_OFFSET,
441 .context_offs = DRA7XX_RM_L4PER2_PWMSS3_CONTEXT_OFFSET,
486 .context_offs = DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
508 .context_offs = DRA7XX_RM_L3MAIN1_TPCC_CONTEXT_OFFSET,
531 .context_offs = DRA7XX_RM_L3MAIN1_TPTC1_CONTEXT_OFFSET,
547 .context_offs = DRA7XX_RM_L3MAIN1_TPTC2_CONTEXT_OFFSET,
590 .context_offs = DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET,
708 .context_offs = DRA7XX_RM_L4SEC_AES1_CONTEXT_OFFSET,
723 .context_offs = DRA7XX_RM_L4SEC_AES2_CONTEXT_OFFSET,
751 .context_offs = DRA7XX_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET,
789 .context_offs = DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET,
831 .context_offs = DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
853 .context_offs = DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
875 .context_offs = DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
897 .context_offs = DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
919 .context_offs = DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
941 .context_offs = DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
963 .context_offs = DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
985 .context_offs = DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
1025 .context_offs = DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET,
1061 .context_offs = DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1101 .context_offs = DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
1117 .context_offs = DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
1133 .context_offs = DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
1149 .context_offs = DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
1165 .context_offs = DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET,
1198 .context_offs = DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET,
1211 .context_offs = DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET,
1224 .context_offs = DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET,
1237 .context_offs = DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET,
1250 .context_offs = DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET,
1263 .context_offs = DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET,
1276 .context_offs = DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET,
1289 .context_offs = DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET,
1302 .context_offs = DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET,
1315 .context_offs = DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET,
1328 .context_offs = DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET,
1341 .context_offs = DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET,
1354 .context_offs = DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET,
1388 .context_offs = DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
1403 .context_offs = DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
1418 .context_offs = DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
1433 .context_offs = DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1471 .context_offs = DRA7XX_RM_IPU_MCASP1_CONTEXT_OFFSET,
1494 .context_offs = DRA7XX_RM_L4PER2_MCASP2_CONTEXT_OFFSET,
1516 .context_offs = DRA7XX_RM_L4PER2_MCASP3_CONTEXT_OFFSET,
1538 .context_offs = DRA7XX_RM_L4PER2_MCASP4_CONTEXT_OFFSET,
1560 .context_offs = DRA7XX_RM_L4PER2_MCASP5_CONTEXT_OFFSET,
1582 .context_offs = DRA7XX_RM_L4PER2_MCASP6_CONTEXT_OFFSET,
1604 .context_offs = DRA7XX_RM_L4PER2_MCASP7_CONTEXT_OFFSET,
1626 .context_offs = DRA7XX_RM_L4PER2_MCASP8_CONTEXT_OFFSET,
1674 .context_offs = DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1696 .context_offs = DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1717 .context_offs = DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
1738 .context_offs = DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
1765 .context_offs = DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET,
1799 .context_offs = DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
1814 .context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
1868 .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,
1891 .context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET,
1925 .context_offs = DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET,
1960 .context_offs = DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET,
1998 .context_offs = DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
2039 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET,
2060 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET,
2097 .context_offs = DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
2148 .context_offs = DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
2163 .context_offs = DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
2178 .context_offs = DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
2193 .context_offs = DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
2208 .context_offs = DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET,
2223 .context_offs = DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET,
2238 .context_offs = DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET,
2253 .context_offs = DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET,
2268 .context_offs = DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
2283 .context_offs = DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
2298 .context_offs = DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
2313 .context_offs = DRA7XX_RM_WKUPAON_TIMER12_CONTEXT_OFFSET,
2327 .context_offs = DRA7XX_RM_L4PER3_TIMER13_CONTEXT_OFFSET,
2342 .context_offs = DRA7XX_RM_L4PER3_TIMER14_CONTEXT_OFFSET,
2357 .context_offs = DRA7XX_RM_L4PER3_TIMER15_CONTEXT_OFFSET,
2372 .context_offs = DRA7XX_RM_L4PER3_TIMER16_CONTEXT_OFFSET,
2410 .context_offs = DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET,
2426 .context_offs = DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET,
2442 .context_offs = DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET,
2458 .context_offs = DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET,
2474 .context_offs = DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET,
2490 .context_offs = DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET,
2506 .context_offs = DRA7XX_RM_L4PER2_UART7_CONTEXT_OFFSET,
2522 .context_offs = DRA7XX_RM_L4PER2_UART8_CONTEXT_OFFSET,
2538 .context_offs = DRA7XX_RM_L4PER2_UART9_CONTEXT_OFFSET,
2554 .context_offs = DRA7XX_RM_WKUPAON_UART10_CONTEXT_OFFSET,
2582 .context_offs = DRA7XX_RM_L4SEC_DES3DES_CONTEXT_OFFSET,
2610 .context_offs = DRA7XX_RM_L4SEC_RNG_CONTEXT_OFFSET,
2651 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET,
2673 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET,
2690 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET,
2705 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET,
2729 .context_offs = DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET,
2743 .context_offs = DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET,
2780 .context_offs = DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,