Lines Matching refs:clkdm_offs

320 	.clkdm_offs	  = DRA7XX_CM_CORE_L4PER_L4PER3_CDOFFS,
330 	.clkdm_offs	  = DRA7XX_CM_CORE_L4PER_L4PER2_CDOFFS,
342 	.clkdm_offs	  = DRA7XX_MPU_PRCM_CM_C0_CPU0_CDOFFS,
351 	.clkdm_offs	  = DRA7XX_CM_CORE_IVA_IVA_CDOFFS,
363 	.clkdm_offs	  = DRA7XX_CM_CORE_COREAON_COREAON_CDOFFS,
372 	.clkdm_offs	  = DRA7XX_CM_CORE_AON_IPU_IPU1_CDOFFS,
384 	.clkdm_offs	  = DRA7XX_CM_CORE_CORE_IPU2_CDOFFS,
396 	.clkdm_offs	  = DRA7XX_CM_CORE_L3INIT_L3INIT_CDOFFS,
408 	.clkdm_offs	  = DRA7XX_CM_CORE_L4PER_L4SEC_CDOFFS,
420 	.clkdm_offs	  = DRA7XX_CM_CORE_CORE_L3MAIN1_CDOFFS,
430 	.clkdm_offs	  = DRA7XX_CM_CORE_AON_VPE_VPE_CDOFFS,
442 	.clkdm_offs	  = DRA7XX_CM_CORE_AON_MPU_MPU_CDOFFS,
453 	.clkdm_offs	  = DRA7XX_CM_CORE_CUSTEFUSE_CUSTEFUSE_CDOFFS,
462 	.clkdm_offs	  = DRA7XX_CM_CORE_AON_IPU_IPU_CDOFFS,
472 	.clkdm_offs	  = DRA7XX_MPU_PRCM_CM_C1_CPU1_CDOFFS,
481 	.clkdm_offs	  = DRA7XX_CM_CORE_L3INIT_GMAC_CDOFFS,
493 	.clkdm_offs	  = DRA7XX_CM_CORE_CORE_L4CFG_CDOFFS,
503 	.clkdm_offs	  = DRA7XX_CM_CORE_CORE_DMA_CDOFFS,
514 	.clkdm_offs	  = DRA7XX_CM_CORE_AON_RTC_RTC_CDOFFS,
523 	.clkdm_offs	  = DRA7XX_CM_CORE_L3INIT_PCIE_CDOFFS,
535 	.clkdm_offs	  = DRA7XX_CM_CORE_CORE_ATL_CDOFFS,
545 	.clkdm_offs	  = DRA7XX_CM_CORE_CORE_L3INSTR_CDOFFS,
553 	.clkdm_offs	  = DRA7XX_CM_CORE_DSS_DSS_CDOFFS,
565 	.clkdm_offs	  = DRA7XX_CM_CORE_CORE_EMIF_CDOFFS,
575 	.clkdm_offs	  = DRA7XX_PRM_EMU_CM_EMU_CDOFFS,
584 	.clkdm_offs	  = DRA7XX_CM_CORE_AON_DSP2_DSP2_CDOFFS,
596 	.clkdm_offs	  = DRA7XX_CM_CORE_AON_DSP1_DSP1_CDOFFS,
608 	.clkdm_offs	  = DRA7XX_CM_CORE_CAM_CAM_CDOFFS,
620 	.clkdm_offs	  = DRA7XX_CM_CORE_L4PER_L4PER_CDOFFS,
630 	.clkdm_offs	  = DRA7XX_CM_CORE_GPU_GPU_CDOFFS,
642 	.clkdm_offs	  = DRA7XX_CM_CORE_AON_EVE4_EVE4_CDOFFS,
654 	.clkdm_offs	  = DRA7XX_CM_CORE_AON_EVE2_EVE2_CDOFFS,
666 	.clkdm_offs	  = DRA7XX_CM_CORE_AON_EVE3_EVE3_CDOFFS,
678 	.clkdm_offs	  = DRA7XX_PRM_WKUPAON_CM_WKUPAON_CDOFFS,
688 	.clkdm_offs	  = DRA7XX_CM_CORE_AON_EVE1_EVE1_CDOFFS,