Lines Matching refs:__raw_writel
250 __raw_writel(status & IOP13XX_ATUX_ATUISR_ERROR, in iop13xx_atux_pci_status()
286 __raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3, in iop13xx_atux_read_config()
315 __raw_writel(val | value << where, IOP13XX_ATUX_OCCDR); in iop13xx_atux_write_config()
317 __raw_writel(addr, IOP13XX_ATUX_OCCAR); in iop13xx_atux_write_config()
318 __raw_writel(value, IOP13XX_ATUX_OCCDR); in iop13xx_atux_write_config()
382 __raw_writel(status, IOP13XX_ATUE_PIE_STS); in iop13xx_atue_pci_status()
407 __raw_writel(addr, IOP13XX_ATUE_OCCAR); in iop13xx_atue_read()
429 __raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3, in iop13xx_atue_read_config()
462 __raw_writel(val | value << where, IOP13XX_ATUE_OCCDR); in iop13xx_atue_write_config()
464 __raw_writel(addr, IOP13XX_ATUE_OCCAR); in iop13xx_atue_write_config()
465 __raw_writel(value, IOP13XX_ATUE_OCCDR); in iop13xx_atue_write_config()
572 __raw_writel(IOP13XX_MU_BASE_PHYS, IOP13XX_MU_MUBAR); in iop13xx_atue_setup()
573 __raw_writel(~(IOP13XX_MU_WINDOW_SIZE - 1), IOP13XX_ATUE_IALR0); in iop13xx_atue_setup()
574 __raw_writel(IOP13XX_MU_BASE_PHYS, IOP13XX_ATUE_IATVR0); in iop13xx_atue_setup()
575 __raw_writel(IOP13XX_MU_BASE_PCI, IOP13XX_ATUE_IABAR0); in iop13xx_atue_setup()
580 __raw_writel(~(IOP13XX_MAX_RAM_SIZE - PHYS_OFFSET - 1) & ~0x1, in iop13xx_atue_setup()
582 __raw_writel(0x0, IOP13XX_ATUE_IAUBAR1); in iop13xx_atue_setup()
585 __raw_writel(PHYS_OFFSET | PCI_BASE_ADDRESS_MEM_TYPE_64 | in iop13xx_atue_setup()
591 __raw_writel(0x0, IOP13XX_ATUE_IAUTVR1); in iop13xx_atue_setup()
592 __raw_writel(PHYS_OFFSET, IOP13XX_ATUE_IATVR1); in iop13xx_atue_setup()
596 __raw_writel(0x0, IOP13XX_ATUE_OUMWTVR1); in iop13xx_atue_setup()
598 __raw_writel(IOP13XX_ATUE_OUMBAR_ENABLE | in iop13xx_atue_setup()
605 __raw_writel(((IOP13XX_PCIE_LOWER_IO_PA >> 0x4) & 0xfffff000), in iop13xx_atue_setup()
607 __raw_writel(IOP13XX_PCIE_LOWER_IO_BA, IOP13XX_ATUE_OIOWTVR); in iop13xx_atue_setup()
617 __raw_writel(reg_val, IOP13XX_ATUE_OIOBAR); in iop13xx_atue_setup()
625 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR0); in iop13xx_atue_setup()
631 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR1); in iop13xx_atue_setup()
637 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR2); in iop13xx_atue_setup()
643 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR3); in iop13xx_atue_setup()
655 __raw_writel(reg_val, IOP13XX_ATUE_ATUCR); in iop13xx_atue_setup()
663 __raw_writel(IOP13XX_ATUE_ATUCR_IVM, IOP13XX_ATUE_ATUCR); in iop13xx_atue_disable()
672 __raw_writel(0x0, IOP13XX_ATUE_IAUBAR0); in iop13xx_atue_disable()
673 __raw_writel(0x0, IOP13XX_ATUE_IABAR0); in iop13xx_atue_disable()
674 __raw_writel(0x0, IOP13XX_ATUE_IAUTVR0); in iop13xx_atue_disable()
675 __raw_writel(0x0, IOP13XX_ATUE_IATVR0); in iop13xx_atue_disable()
676 __raw_writel(0x0, IOP13XX_ATUE_IALR0); in iop13xx_atue_disable()
679 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR0); in iop13xx_atue_disable()
682 __raw_writel(0x0, IOP13XX_ATUE_IAUBAR1); in iop13xx_atue_disable()
683 __raw_writel(0x0, IOP13XX_ATUE_IABAR1); in iop13xx_atue_disable()
684 __raw_writel(0x0, IOP13XX_ATUE_IAUTVR1); in iop13xx_atue_disable()
685 __raw_writel(0x0, IOP13XX_ATUE_IATVR1); in iop13xx_atue_disable()
686 __raw_writel(0x0, IOP13XX_ATUE_IALR1); in iop13xx_atue_disable()
689 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR1); in iop13xx_atue_disable()
692 __raw_writel(0x0, IOP13XX_ATUE_IAUBAR2); in iop13xx_atue_disable()
693 __raw_writel(0x0, IOP13XX_ATUE_IABAR2); in iop13xx_atue_disable()
694 __raw_writel(0x0, IOP13XX_ATUE_IAUTVR2); in iop13xx_atue_disable()
695 __raw_writel(0x0, IOP13XX_ATUE_IATVR2); in iop13xx_atue_disable()
696 __raw_writel(0x0, IOP13XX_ATUE_IALR2); in iop13xx_atue_disable()
699 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR2); in iop13xx_atue_disable()
704 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR3); in iop13xx_atue_disable()
709 __raw_writel((IOP13XX_PCIE_LOWER_IO_PA >> 0x4) & 0xfffff000, in iop13xx_atue_disable()
711 __raw_writel(IOP13XX_PCIE_LOWER_IO_BA, IOP13XX_ATUE_OIOWTVR); in iop13xx_atue_disable()
732 __raw_writel(reg_val & ~IOP13XX_ATUX_PCSR_P_RSTOUT, in iop13xx_atux_setup()
741 __raw_writel(IOP13XX_MU_BASE_PHYS, IOP13XX_MU_MUBAR); in iop13xx_atux_setup()
742 __raw_writel(~(IOP13XX_MU_WINDOW_SIZE - 1), IOP13XX_ATUX_IALR0); in iop13xx_atux_setup()
743 __raw_writel(IOP13XX_MU_BASE_PHYS, IOP13XX_ATUX_IATVR0); in iop13xx_atux_setup()
744 __raw_writel(IOP13XX_MU_BASE_PCI, IOP13XX_ATUX_IABAR0); in iop13xx_atux_setup()
749 __raw_writel(~(IOP13XX_MAX_RAM_SIZE - PHYS_OFFSET - 1) & ~0x1, in iop13xx_atux_setup()
751 __raw_writel(0x0, IOP13XX_ATUX_IAUBAR1); in iop13xx_atux_setup()
754 __raw_writel(PHYS_OFFSET | PCI_BASE_ADDRESS_MEM_TYPE_64 | in iop13xx_atux_setup()
760 __raw_writel(0x0, IOP13XX_ATUX_IAUTVR1); in iop13xx_atux_setup()
761 __raw_writel(PHYS_OFFSET, IOP13XX_ATUX_IATVR1); in iop13xx_atux_setup()
765 __raw_writel(0x0, IOP13XX_ATUX_OUMWTVR1); in iop13xx_atux_setup()
767 __raw_writel(IOP13XX_ATUX_OUMBAR_ENABLE | in iop13xx_atux_setup()
774 __raw_writel((IOP13XX_PCIX_LOWER_IO_PA >> 0x4) & 0xfffff000, in iop13xx_atux_setup()
776 __raw_writel(IOP13XX_PCIX_LOWER_IO_BA, IOP13XX_ATUX_OIOWTVR); in iop13xx_atux_setup()
786 __raw_writel(reg_val, IOP13XX_ATUX_OIOBAR); in iop13xx_atux_setup()
794 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR0); in iop13xx_atux_setup()
800 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR1); in iop13xx_atux_setup()
806 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR2); in iop13xx_atux_setup()
812 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR3); in iop13xx_atux_setup()
823 __raw_writel(reg_val, IOP13XX_ATUX_ATUCR); in iop13xx_atux_setup()
831 __raw_writel(0x0, IOP13XX_ATUX_ATUCR); in iop13xx_atux_disable()
839 __raw_writel(0x0, IOP13XX_ATUX_IAUBAR0); in iop13xx_atux_disable()
840 __raw_writel(0x0, IOP13XX_ATUX_IABAR0); in iop13xx_atux_disable()
841 __raw_writel(0x0, IOP13XX_ATUX_IAUTVR0); in iop13xx_atux_disable()
842 __raw_writel(0x0, IOP13XX_ATUX_IATVR0); in iop13xx_atux_disable()
843 __raw_writel(0x0, IOP13XX_ATUX_IALR0); in iop13xx_atux_disable()
846 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR0); in iop13xx_atux_disable()
849 __raw_writel(0x0, IOP13XX_ATUX_IAUBAR1); in iop13xx_atux_disable()
850 __raw_writel(0x0, IOP13XX_ATUX_IABAR1); in iop13xx_atux_disable()
851 __raw_writel(0x0, IOP13XX_ATUX_IAUTVR1); in iop13xx_atux_disable()
852 __raw_writel(0x0, IOP13XX_ATUX_IATVR1); in iop13xx_atux_disable()
853 __raw_writel(0x0, IOP13XX_ATUX_IALR1); in iop13xx_atux_disable()
856 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR1); in iop13xx_atux_disable()
859 __raw_writel(0x0, IOP13XX_ATUX_IAUBAR2); in iop13xx_atux_disable()
860 __raw_writel(0x0, IOP13XX_ATUX_IABAR2); in iop13xx_atux_disable()
861 __raw_writel(0x0, IOP13XX_ATUX_IAUTVR2); in iop13xx_atux_disable()
862 __raw_writel(0x0, IOP13XX_ATUX_IATVR2); in iop13xx_atux_disable()
863 __raw_writel(0x0, IOP13XX_ATUX_IALR2); in iop13xx_atux_disable()
866 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR2); in iop13xx_atux_disable()
869 __raw_writel(0x0, IOP13XX_ATUX_IAUBAR3); in iop13xx_atux_disable()
870 __raw_writel(0x0, IOP13XX_ATUX_IABAR3); in iop13xx_atux_disable()
871 __raw_writel(0x0, IOP13XX_ATUX_IAUTVR3); in iop13xx_atux_disable()
872 __raw_writel(0x0, IOP13XX_ATUX_IATVR3); in iop13xx_atux_disable()
873 __raw_writel(0x0, IOP13XX_ATUX_IALR3); in iop13xx_atux_disable()
876 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR3); in iop13xx_atux_disable()
881 __raw_writel((IOP13XX_PCIX_LOWER_IO_PA >> 0x4) & 0xfffff000, in iop13xx_atux_disable()
883 __raw_writel(IOP13XX_PCIX_LOWER_IO_BA, IOP13XX_ATUX_OIOWTVR); in iop13xx_atux_disable()
977 __raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3, IOP13XX_XBG_BECSR); in iop13xx_pci_init()
1049 __raw_writel(pcixsr, IOP13XX_ATUX_PCIXSR); in iop13xx_pci_setup()
1066 __raw_writel(pcsr, IOP13XX_ATUE_PCSR); in iop13xx_pci_setup()