Lines Matching refs:end
157 .end = DA8XX_TPCC_BASE + SZ_32K - 1,
163 .end = DA8XX_TPTC0_BASE + SZ_1K - 1,
169 .end = DA8XX_TPTC1_BASE + SZ_1K - 1,
188 .end = DA850_TPCC1_BASE + SZ_32K - 1,
194 .end = DA850_TPTC2_BASE + SZ_1K - 1,
305 .end = DA8XX_I2C0_BASE + SZ_4K - 1,
310 .end = IRQ_DA8XX_I2CINT0,
325 .end = DA8XX_I2C1_BASE + SZ_4K - 1,
330 .end = IRQ_DA8XX_I2CINT1,
361 .end = DA8XX_WDOG_BASE + SZ_4K - 1,
381 .end = DA8XX_EMAC_CPPI_PORT_BASE + SZ_16K - 1,
386 .end = IRQ_DA8XX_C0_RX_THRESH_PULSE,
391 .end = IRQ_DA8XX_C0_RX_PULSE,
396 .end = IRQ_DA8XX_C0_TX_PULSE,
401 .end = IRQ_DA8XX_C0_MISC_PULSE,
427 .end = DA8XX_EMAC_MDIO_BASE + SZ_4K - 1,
454 .end = DAVINCI_DA830_MCASP1_REG_BASE + (SZ_1K * 12) - 1,
461 .end = DAVINCI_DA830_DMA_MCASP1_AXEVT,
468 .end = DAVINCI_DA830_DMA_MCASP1_AREVT,
489 .end = DAVINCI_DA830_MCASP2_REG_BASE + (SZ_1K * 12) - 1,
496 .end = DAVINCI_DA830_DMA_MCASP2_AXEVT,
503 .end = DAVINCI_DA830_DMA_MCASP2_AREVT,
524 .end = DAVINCI_DA8XX_MCASP0_REG_BASE + (SZ_1K * 12) - 1,
531 .end = DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
538 .end = DAVINCI_DA8XX_DMA_MCASP0_AREVT,
587 .end = DA8XX_PRUSS_MEM_BASE + 0xFFFF,
592 .end = IRQ_DA8XX_EVTOUT0,
597 .end = IRQ_DA8XX_EVTOUT1,
602 .end = IRQ_DA8XX_EVTOUT2,
607 .end = IRQ_DA8XX_EVTOUT3,
612 .end = IRQ_DA8XX_EVTOUT4,
617 .end = IRQ_DA8XX_EVTOUT5,
622 .end = IRQ_DA8XX_EVTOUT6,
627 .end = IRQ_DA8XX_EVTOUT7,
673 .end = DA8XX_LCD_CNTRL_BASE + SZ_4K - 1,
678 .end = IRQ_DA8XX_LCDINT,
699 .end = DA8XX_GPIO_BASE + SZ_4K - 1,
704 .end = IRQ_DA8XX_GPIO8,
725 .end = DA8XX_MMCSD0_BASE + SZ_4K - 1,
730 .end = IRQ_DA8XX_MMCSDINT0,
752 .end = DA850_MMCSD1_BASE + SZ_4K - 1,
757 .end = IRQ_DA850_MMCSDINT0_1,
780 .end = DA8XX_SYSCFG0_BASE + DA8XX_HOST1CFG_REG + 3,
786 .end = DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG + 7,
792 .end = DA8XX_DSP_L2_RAM_BASE + SZ_256K - 1,
798 .end = DA8XX_DSP_L1P_RAM_BASE + SZ_32K - 1,
804 .end = DA8XX_DSP_L1D_RAM_BASE + SZ_32K - 1,
809 .end = IRQ_DA8XX_CHIPINT0,
895 .end = DA8XX_RTC_BASE + SZ_4K - 1,
900 .end = IRQ_DA8XX_RTC,
905 .end = IRQ_DA8XX_RTC,
938 .end = DA8XX_DDR2_CTL_BASE + SZ_32K - 1,
968 .end = DA8XX_SPI0_BASE + SZ_4K - 1,
973 .end = IRQ_DA8XX_SPINT0,
981 .end = DA830_SPI1_BASE + SZ_4K - 1,
986 .end = IRQ_DA8XX_SPINT1,
1036 da8xx_spi1_resources[0].end = DA850_SPI1_BASE + SZ_4K - 1; in da8xx_register_spi_bus()
1057 .end = DA850_SATA_BASE + 0x1fff,
1062 .end = DA8XX_SYSCFG1_BASE + DA8XX_PWRDN_REG + 0x3,