Lines Matching refs:ccu
50 #include <dt-bindings/clock/sun6i-a31-ccu.h>
51 #include <dt-bindings/reset/sun6i-a31-ccu.h>
69 clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>,
70 <&ccu CLK_AHB1_HDMI>, <&ccu CLK_DRAM_BE0>,
71 <&ccu CLK_IEP_DRC0>, <&ccu CLK_BE0>,
72 <&ccu CLK_LCD0_CH1>, <&ccu CLK_HDMI>;
80 clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>,
81 <&ccu CLK_DRAM_BE0>, <&ccu CLK_IEP_DRC0>,
82 <&ccu CLK_BE0>, <&ccu CLK_LCD0_CH0>;
106 clocks = <&ccu CLK_CPU>;
122 clocks = <&ccu CLK_CPU>;
138 clocks = <&ccu CLK_CPU>;
154 clocks = <&ccu CLK_CPU>;
277 clocks = <&ccu CLK_AHB1_DMA>;
278 resets = <&ccu RST_AHB1_DMA>;
286 resets = <&ccu RST_AHB1_LCD0>;
288 clocks = <&ccu CLK_AHB1_LCD0>,
289 <&ccu CLK_LCD0_CH0>,
290 <&ccu CLK_LCD0_CH1>;
334 resets = <&ccu RST_AHB1_LCD1>;
336 clocks = <&ccu CLK_AHB1_LCD1>,
337 <&ccu CLK_LCD1_CH0>,
338 <&ccu CLK_LCD1_CH1>;
381 clocks = <&ccu CLK_AHB1_MMC0>,
382 <&ccu CLK_MMC0>,
383 <&ccu CLK_MMC0_OUTPUT>,
384 <&ccu CLK_MMC0_SAMPLE>;
389 resets = <&ccu RST_AHB1_MMC0>;
400 clocks = <&ccu CLK_AHB1_MMC1>,
401 <&ccu CLK_MMC1>,
402 <&ccu CLK_MMC1_OUTPUT>,
403 <&ccu CLK_MMC1_SAMPLE>;
408 resets = <&ccu RST_AHB1_MMC1>;
419 clocks = <&ccu CLK_AHB1_MMC2>,
420 <&ccu CLK_MMC2>,
421 <&ccu CLK_MMC2_OUTPUT>,
422 <&ccu CLK_MMC2_SAMPLE>;
427 resets = <&ccu RST_AHB1_MMC2>;
438 clocks = <&ccu CLK_AHB1_MMC3>,
439 <&ccu CLK_MMC3>,
440 <&ccu CLK_MMC3_OUTPUT>,
441 <&ccu CLK_MMC3_SAMPLE>;
446 resets = <&ccu RST_AHB1_MMC3>;
458 clocks = <&ccu CLK_AHB1_HDMI>, <&ccu CLK_HDMI>,
459 <&ccu CLK_HDMI_DDC>,
460 <&ccu CLK_PLL_VIDEO0_2X>,
461 <&ccu CLK_PLL_VIDEO1_2X>;
463 resets = <&ccu RST_AHB1_HDMI>;
500 clocks = <&ccu CLK_AHB1_OTG>;
501 resets = <&ccu RST_AHB1_OTG>;
518 clocks = <&ccu CLK_USB_PHY0>,
519 <&ccu CLK_USB_PHY1>,
520 <&ccu CLK_USB_PHY2>;
524 resets = <&ccu RST_USB_PHY0>,
525 <&ccu RST_USB_PHY1>,
526 <&ccu RST_USB_PHY2>;
538 clocks = <&ccu CLK_AHB1_EHCI0>;
539 resets = <&ccu RST_AHB1_EHCI0>;
549 clocks = <&ccu CLK_AHB1_OHCI0>, <&ccu CLK_USB_OHCI0>;
550 resets = <&ccu RST_AHB1_OHCI0>;
560 clocks = <&ccu CLK_AHB1_EHCI1>;
561 resets = <&ccu RST_AHB1_EHCI1>;
571 clocks = <&ccu CLK_AHB1_OHCI1>, <&ccu CLK_USB_OHCI1>;
572 resets = <&ccu RST_AHB1_OHCI1>;
582 clocks = <&ccu CLK_AHB1_OHCI2>, <&ccu CLK_USB_OHCI2>;
583 resets = <&ccu RST_AHB1_OHCI2>;
587 ccu: clock@1c20000 { label
588 compatible = "allwinner,sun6i-a31-ccu";
603 clocks = <&ccu CLK_APB1_PIO>, <&osc24M>, <&osc32k>;
750 clocks = <&ccu CLK_APB1_SPDIF>, <&ccu CLK_SPDIF>;
751 resets = <&ccu RST_APB1_SPDIF>;
763 clocks = <&ccu CLK_APB1_DAUDIO0>, <&ccu CLK_DAUDIO0>;
764 resets = <&ccu RST_APB1_DAUDIO0>;
776 clocks = <&ccu CLK_APB1_DAUDIO1>, <&ccu CLK_DAUDIO1>;
777 resets = <&ccu RST_APB1_DAUDIO1>;
804 clocks = <&ccu CLK_APB2_UART0>;
805 resets = <&ccu RST_APB2_UART0>;
817 clocks = <&ccu CLK_APB2_UART1>;
818 resets = <&ccu RST_APB2_UART1>;
830 clocks = <&ccu CLK_APB2_UART2>;
831 resets = <&ccu RST_APB2_UART2>;
843 clocks = <&ccu CLK_APB2_UART3>;
844 resets = <&ccu RST_APB2_UART3>;
856 clocks = <&ccu CLK_APB2_UART4>;
857 resets = <&ccu RST_APB2_UART4>;
869 clocks = <&ccu CLK_APB2_UART5>;
870 resets = <&ccu RST_APB2_UART5>;
880 clocks = <&ccu CLK_APB2_I2C0>;
881 resets = <&ccu RST_APB2_I2C0>;
891 clocks = <&ccu CLK_APB2_I2C1>;
892 resets = <&ccu RST_APB2_I2C1>;
902 clocks = <&ccu CLK_APB2_I2C2>;
903 resets = <&ccu RST_APB2_I2C2>;
913 clocks = <&ccu CLK_APB2_I2C3>;
914 resets = <&ccu RST_APB2_I2C3>;
925 clocks = <&ccu CLK_AHB1_EMAC>, <&gmac_tx_clk>;
927 resets = <&ccu RST_AHB1_EMAC>;
942 clocks = <&ccu CLK_AHB1_SS>, <&ccu CLK_SS>;
944 resets = <&ccu RST_AHB1_SS>;
953 clocks = <&ccu CLK_APB1_CODEC>, <&ccu CLK_CODEC>;
955 resets = <&ccu RST_APB1_CODEC>;
969 clocks = <&ccu CLK_AHB1_HSTIMER>;
970 resets = <&ccu RST_AHB1_HSTIMER>;
977 clocks = <&ccu CLK_AHB1_SPI0>, <&ccu CLK_SPI0>;
981 resets = <&ccu RST_AHB1_SPI0>;
989 clocks = <&ccu CLK_AHB1_SPI1>, <&ccu CLK_SPI1>;
993 resets = <&ccu RST_AHB1_SPI1>;
1001 clocks = <&ccu CLK_AHB1_SPI2>, <&ccu CLK_SPI2>;
1005 resets = <&ccu RST_AHB1_SPI2>;
1013 clocks = <&ccu CLK_AHB1_SPI3>, <&ccu CLK_SPI3>;
1017 resets = <&ccu RST_AHB1_SPI3>;
1036 clocks = <&ccu CLK_AHB1_FE0>, <&ccu CLK_FE0>,
1037 <&ccu CLK_DRAM_FE0>;
1040 resets = <&ccu RST_AHB1_FE0>;
1068 clocks = <&ccu CLK_AHB1_FE1>, <&ccu CLK_FE1>,
1069 <&ccu CLK_DRAM_FE1>;
1072 resets = <&ccu RST_AHB1_FE1>;
1100 clocks = <&ccu CLK_AHB1_BE1>, <&ccu CLK_BE1>,
1101 <&ccu CLK_DRAM_BE1>;
1104 resets = <&ccu RST_AHB1_BE1>;
1106 assigned-clocks = <&ccu CLK_BE1>;
1146 clocks = <&ccu CLK_AHB1_DRC1>, <&ccu CLK_IEP_DRC1>,
1147 <&ccu CLK_DRAM_DRC1>;
1150 resets = <&ccu RST_AHB1_DRC1>;
1152 assigned-clocks = <&ccu CLK_IEP_DRC1>;
1192 clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_BE0>,
1193 <&ccu CLK_DRAM_BE0>;
1196 resets = <&ccu RST_AHB1_BE0>;
1198 assigned-clocks = <&ccu CLK_BE0>;
1238 clocks = <&ccu CLK_AHB1_DRC0>, <&ccu CLK_IEP_DRC0>,
1239 <&ccu CLK_DRAM_DRC0>;
1242 resets = <&ccu RST_AHB1_DRC0>;
1244 assigned-clocks = <&ccu CLK_IEP_DRC0>;
1303 <&ccu CLK_PLL_PERIPH>,
1304 <&ccu CLK_PLL_PERIPH>;