Lines Matching refs:rcc
51 #include <dt-bindings/mfd/stm32f4-rcc.h>
85 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
94 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
114 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
123 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
143 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
152 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
172 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
180 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
200 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
209 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
224 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
233 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
249 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM12)>;
270 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>;
285 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>;
298 clocks = <&rcc 1 CLK_RTC>;
300 assigned-clocks = <&rcc 1 CLK_RTC>;
301 assigned-clock-parents = <&rcc 1 CLK_LSE>;
321 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART2)>;
329 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART3)>;
340 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART4)>;
348 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART5)>;
357 resets = <&rcc STM32F4_APB1_RESET(I2C1)>;
358 clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C1)>;
367 resets = <&rcc STM32F4_APB1_RESET(DAC)>;
368 clocks = <&rcc 0 STM32F4_APB1_CLOCK(DAC)>;
393 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART7)>;
401 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART8)>;
410 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM1)>;
431 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM8)>;
451 clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART1)>;
462 clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART6)>;
470 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
482 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
494 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC2)>;
506 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC3)>;
519 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SDIO)>;
544 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM9)>;
565 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>;
580 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>;
599 resets = <&rcc STM32F4_APB2_RESET(LTDC)>;
600 clocks = <&rcc 1 CLK_LCD>;
608 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(CRC)>;
612 rcc: rcc@40023810 { label
615 compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
619 assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
634 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA1)>;
649 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2)>;
661 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(ETHMAC)>,
662 <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACTX)>,
663 <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACRX)>;
674 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHS)>;
683 clocks = <&rcc 0 39>;
692 resets = <&rcc STM32F4_AHB2_RESET(DCMI)>;
693 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(DCMI)>;
706 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(RNG)>;
713 clocks = <&rcc 1 SYSTICK>;