Lines Matching refs:c0
35 mcr p14, 0, \ch, c0, c5, 0
41 mcr p14, 0, \ch, c8, c0, 0
47 mcr p14, 0, \ch, c1, c0, 0
95 mrc p15, 0, r0, c1, c0
638 mcr p15, 0, r0, c2, c0, 0 @ D-cache on
639 mcr p15, 0, r0, c2, c0, 1 @ I-cache on
640 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
643 mcr p15, 0, r0, c5, c0, 1 @ I-access permission
644 mcr p15, 0, r0, c5, c0, 0 @ D-access permission
650 mrc p15, 0, r0, c1, c0, 0 @ read control reg
655 mcr p15, 0, r0, c1, c0, 0 @ write control reg
667 mcr p15, 0, r0, c2, c0, 0 @ cache on
668 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
671 mcr p15, 0, r0, c5, c0, 0 @ access permission
674 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
679 mrc p15, 0, r0, c1, c0, 0 @ read control reg
684 mcr p15, 0, r0, c1, c0, 0 @ write control reg
687 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
740 mrc p15, 0, r0, c1, c0, 0 @ read SCTLR
743 mcr p15, 0, r0, c1, c0, 0 @ write SCTLR
749 mcr p15, 7, r0, c15, c0, 0
760 mrc p15, 0, r0, c1, c0, 0 @ read control reg
773 mrc p15, 0, r11, c0, c1, 4 @ read ID_MMFR0
782 mrc p15, 0, r0, c1, c0, 0 @ read control reg
791 mrcne p15, 0, r6, c2, c0, 2 @ read ttb control reg
796 mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer
797 mcrne p15, 0, r1, c3, c0, 0 @ load domain access control
798 mcrne p15, 0, r6, c2, c0, 2 @ load ttb control
801 mcr p15, 0, r0, c1, c0, 0 @ load control register
802 mrc p15, 0, r0, c1, c0, 0 @ and read it back
815 mrc p15, 0, r0, c1, c0, 0 @ read control reg
828 mcr p15, 0, r3, c2, c0, 0 @ load page table pointer
829 mcr p15, 0, r1, c3, c0, 0 @ load domain access control
832 1: mcr p15, 0, r0, c1, c0, 0 @ load control register
833 mrc p15, 0, r0, c1, c0, 0 @ and read it back to
855 mrc p15, 0, r9, c0, c0 @ get processor ID
1062 mrc p15, 0, r0, c1, c0
1064 mcr p15, 0, r0, c1, c0 @ turn MPU and cache off
1072 mrc p15, 0, r0, c1, c0
1074 mcr p15, 0, r0, c1, c0, 0 @ turn MPU and cache off
1076 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
1081 mrc p15, 0, r0, c1, c0
1083 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1091 mrc p15, 0, r0, c1, c0
1097 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1162 mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1
1171 mrc p15, 1, r0, c0, c0, 1 @ read clidr
1182 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
1184 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
1213 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
1235 mrc p15, 0, r3, c0, c0, 1 @ read cache type
1269 mcr p15, 0, r1, c7, c0, 0 @ invalidate whole cache v3