Lines Matching refs:erratum

956 	  fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
965 	  r1p* erratum. If a code sequence containing an ARM/Thumb
982 	  erratum. For very specific sequences of memory operations, it is
996 	  erratum. Any asynchronous access to the L2 cache may encounter a
1009 	  (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1022 	  (r2p0..r2p2) erratum. Under certain conditions, specific to the
1037 	  r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1047 	  r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1049 	  As a consequence of this erratum, some TLB entries which should be
1060 	  (r2p*) erratum. Under very rare conditions, a faulty
1074 	  to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1084 	  r3p*) erratum. A speculative memory access may cause a page table walk
1095 	  r2p0) erratum. The Store Buffer does not have any automatic draining
1106 	  r0p2 erratum (possible cache data corruption with
1117 	  This option enables the workaround for erratum 764369
1132 	 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1143 	  option enables the Linux kernel workaround for this erratum
1152 	  (up to r0p4) erratum. In certain rare sequences of code, the
1154 	  workaround disables the loop buffer to avoid the erratum.
1175 	  (all revs) erratum. In very rare timing conditions, a sequence
1185 	  (all revs) erratum. Within rare timing constraints, executing a
1194 	  (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,
1206 	  This is identical to Cortex-A12 erratum 852422.  It is a separate
1207 	  config option from the A12 erratum due to the way errata are checked