Lines Matching refs:errata
943 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
952 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
961 bool "ARM errata: Stale prediction on replaced interworking branch"
977 bool "ARM errata: Processor deadlock when a false hazard is created"
991 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1004 bool "ARM errata: DMB operation may be faulty"
1017 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1032 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1043 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1055 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1069 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1080 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1091 bool "ARM errata: no automatic Store Buffer drain"
1102 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1114 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1128 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1138 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1148 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1157 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
1166 This workaround for all both errata involves setting bit[12] of the
1171 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
1181 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
1190 bool "ARM errata: A17: DMB ST might fail to create order between stores"
1199 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
1207 config option from the A12 erratum due to the way errata are checked