270 		write_aux_reg(aux_cmd, paddr);  in __cache_line_loop_v2()
316 		write_aux_reg(aux_tag, paddr);  in __cache_line_loop_v3()
326 		write_aux_reg(ARC_REG_IC_PTAG_HI, (u64)paddr >> 32);  in __cache_line_loop_v3()
330 			write_aux_reg(aux_tag, paddr);  in __cache_line_loop_v3()
334 		write_aux_reg(aux_cmd, vaddr);  in __cache_line_loop_v3()
392 			write_aux_reg(ARC_REG_IC_PTAG_HI, (u64)paddr >> 32);  in __cache_line_loop_v4()
394 			write_aux_reg(ARC_REG_DC_PTAG_HI, (u64)paddr >> 32);  in __cache_line_loop_v4()
398 		write_aux_reg(aux_cmd, paddr);  in __cache_line_loop_v4()
438 			write_aux_reg(ARC_REG_IC_PTAG_HI, (u64)paddr >> 32);  in __cache_line_loop_v4()
440 			write_aux_reg(ARC_REG_DC_PTAG_HI, (u64)paddr >> 32);  in __cache_line_loop_v4()
444 	write_aux_reg(e, paddr + sz);	/* ENDR is exclusive */  in __cache_line_loop_v4()
445 	write_aux_reg(s, paddr);  in __cache_line_loop_v4()
480 		write_aux_reg(ctl, read_aux_reg(ctl) | DC_CTRL_INV_MODE_FLUSH);  in __before_dc_op()
504 	write_aux_reg(ctl, val);  in __before_dc_op()
522 			write_aux_reg(ctl, reg & ~DC_CTRL_INV_MODE_FLUSH);  in __after_dc_op()
543 	write_aux_reg(aux, 0x1);  in __dc_entire_op()
553 	write_aux_reg(r, read_aux_reg(r) | DC_CTRL_DIS);  in __dc_disable()
560 	write_aux_reg(r, read_aux_reg(r) & ~DC_CTRL_DIS);  in __dc_enable()
600 	write_aux_reg(ARC_REG_IC_IVIC, 1);  in __ic_entire_inv()
691 	write_aux_reg(ARC_REG_SLC_CTRL, ctrl);  in slc_op_rgn()
700 		write_aux_reg(ARC_REG_SLC_RGN_END1, upper_32_bits(end));  in slc_op_rgn()
702 	write_aux_reg(ARC_REG_SLC_RGN_END, lower_32_bits(end));  in slc_op_rgn()
705 		write_aux_reg(ARC_REG_SLC_RGN_START1, upper_32_bits(paddr));  in slc_op_rgn()
707 	write_aux_reg(ARC_REG_SLC_RGN_START, lower_32_bits(paddr));  in slc_op_rgn()
745 	write_aux_reg(ARC_REG_SLC_CTRL, ctrl);  in slc_op_line()
755 		write_aux_reg(cmd, paddr);  in slc_op_line()
781 	write_aux_reg(r, ctrl);  in slc_entire_op()
784 		write_aux_reg(ARC_REG_SLC_INVALIDATE, 0x1);  in slc_entire_op()
786 		write_aux_reg(ARC_REG_SLC_FLUSH, 0x1);  in slc_entire_op()
800 	write_aux_reg(r, read_aux_reg(r) | SLC_CTRL_DIS);  in arc_slc_disable()
807 	write_aux_reg(r, read_aux_reg(r) & ~SLC_CTRL_DIS);  in arc_slc_enable()
1181 	write_aux_reg(ARC_REG_IO_COH_AP0_SIZE, order_base_2(mem_sz >> 10) - 2);  in arc_ioc_setup()
1189 	write_aux_reg(ARC_REG_IO_COH_AP0_BASE, ioc_base >> 12);  in arc_ioc_setup()
1190 	write_aux_reg(ARC_REG_IO_COH_PARTIAL, 1);  in arc_ioc_setup()
1191 	write_aux_reg(ARC_REG_IO_COH_ENABLE, 1);  in arc_ioc_setup()
1308 			write_aux_reg(ARC_REG_IC_PTAG_HI, 0);  in arc_cache_init()
1311 			write_aux_reg(ARC_REG_DC_PTAG_HI, 0);  in arc_cache_init()
1314 			write_aux_reg(ARC_REG_SLC_RGN_END1, 0);  in arc_cache_init()
1315 			write_aux_reg(ARC_REG_SLC_RGN_START1, 0);  in arc_cache_init()