94 	write_aux_reg(ARC_REG_PCT_INDEX, idx);  in arc_pmu_read_counter()
96 	write_aux_reg(ARC_REG_PCT_CONTROL, tmp | ARC_REG_PCT_CONTROL_SN);  in arc_pmu_read_counter()
205 	write_aux_reg(ARC_REG_PCT_CONTROL, (tmp & 0xffff0000) | 0x1);  in arc_pmu_enable()
213 	write_aux_reg(ARC_REG_PCT_CONTROL, (tmp & 0xffff0000) | 0x0);  in arc_pmu_disable()
246 	write_aux_reg(ARC_REG_PCT_INDEX, idx);  in arc_pmu_event_set_period()
249 	write_aux_reg(ARC_REG_PCT_COUNTL, (u32)value);  in arc_pmu_event_set_period()
250 	write_aux_reg(ARC_REG_PCT_COUNTH, (value >> 32));  in arc_pmu_event_set_period()
279 		write_aux_reg(ARC_REG_PCT_INT_CTRL,  in arc_pmu_start()
283 	write_aux_reg(ARC_REG_PCT_INDEX, idx);		/* counter # */  in arc_pmu_start()
284 	write_aux_reg(ARC_REG_PCT_CONFIG, hwc->config);	/* condition */  in arc_pmu_start()
298 		write_aux_reg(ARC_REG_PCT_INT_ACT, 1 << idx);  in arc_pmu_stop()
299 		write_aux_reg(ARC_REG_PCT_INT_CTRL,  in arc_pmu_stop()
305 		write_aux_reg(ARC_REG_PCT_INDEX, idx);  in arc_pmu_stop()
308 		write_aux_reg(ARC_REG_PCT_CONFIG, 0);  in arc_pmu_stop()
346 	write_aux_reg(ARC_REG_PCT_INDEX, idx);  in arc_pmu_add()
352 		write_aux_reg(ARC_REG_PCT_INT_CNTL, (u32)arc_pmu->max_period);  in arc_pmu_add()
353 		write_aux_reg(ARC_REG_PCT_INT_CNTH,  in arc_pmu_add()
357 	write_aux_reg(ARC_REG_PCT_CONFIG, 0);  in arc_pmu_add()
358 	write_aux_reg(ARC_REG_PCT_COUNTL, 0);  in arc_pmu_add()
359 	write_aux_reg(ARC_REG_PCT_COUNTH, 0);  in arc_pmu_add()
395 		write_aux_reg(ARC_REG_PCT_INT_ACT, 1 << idx);  in arc_pmu_intr()
402 		write_aux_reg(ARC_REG_PCT_INT_CTRL,  in arc_pmu_intr()
441 	write_aux_reg(ARC_REG_PCT_INT_ACT, 0xffffffff);  in arc_cpu_pmu_irq_init()
492 		write_aux_reg(ARC_REG_CC_INDEX, j);  in arc_pmu_device_probe()