Lines Matching refs:L2
155 ; if L2 IRQ interrupted a L1 ISR, disable preemption
157 ; This is to avoid a potential L1-L2-L1 scenario
159 ; -L2 interrupts L1 (before L1 ISR could run)
162 ; Returns from L2 context fine
163 ; But both L1 and L2 re-enabled, so another L1 can be taken
168 ; L2 interrupting L1 implies both L2 and L1 active
173 bbit0 r9, STATUS_A1_BIT, 1f ; L1 not active when L2 IRQ, so normal
212 ; out of the L2 interrupt context (drop to pure kernel mode) and jump
338 ; use the same priority as rtie: EXCPN, L2 IRQ, L1 IRQ, None
353 ; However the context returning might not have taken L2 intr itself
354 ; e.g. Task'A' user-code -> L2 intr -> schedule -> 'B' user-code ret
355 ; Special considerations needed for the context which took L2 intr
357 ld r9, [sp, PT_event] ; Ensure this is L2 intr context
361 ; if L2 IRQ interrupted an L1 ISR, we'd disabled preemption earlier
364 ; things to what they were, before returning from L2 context
368 bbit0 r9, STATUS_A1_BIT, 149f ; L1 not active when L2 IRQ, so normal