Lines Matching refs:CPU
1 Coresight CPU Debug Module
10 Coresight CPU debug module is defined in ARMv8-a architecture reference manual
11 (ARM DDI 0487A.k) Chapter 'Part H: External debug', the CPU can integrate
19 to sample CPU program counter, secure state and exception level, etc; usually
20 every CPU has one dedicated debug module to be connected. Based on self-hosted
23 will dump related registers for every CPU; finally this is good for assistant
42 - The driver supports a CPU running in either AArch64 or AArch32 mode. The
53 instruction set state". For ARMv7-a, the driver checks furthermore if CPU
60 state". So on ARMv8 if EDDEVID1.PCSROffset is 0b0010 and the CPU operates
61 in AArch32 state, EDPCSR is not sampled; when the CPU operates in AArch64
71 domain and the CPU domain.
78 | Debug |**| CPU |
90 For CPU domain, the different SoC designs have different power management
95 respect to CPU power domain, the CPU power domain can be controlled by
97 to power up the CPU, and then writes bit EDPRCR.CORENPDRQ for emulation
98 of CPU power down. As result, this can ensure the CPU power domain is
110 is a recipe for disaster; so we need preventing CPU low power states at boot
144 firstly constraint CPU idle states before enable CPU debugging feature; so can
152 It is possible to disable CPU idle states by way of the PM QoS
167 Disable specific CPU's specific idle state from cpuidle sysfs (see
178 coresight-cpu-debug 850000.debug: CPU[0]:
183 coresight-cpu-debug 852000.debug: CPU[1]: