Lines Matching refs:VF
160 PCI devices, but the BARs in VF config space headers are unusual. For
161 a non-VF device, software uses BARs in the config space header to
162 discover the BAR sizes and assign addresses for them. For VF devices,
163 software uses VF BAR registers in the *PF* SR-IOV Capability to
164 discover sizes and assign addresses. The BARs in the VF's config space
167 When a VF BAR in the PF SR-IOV Capability is programmed, it sets the
168 base address for all the corresponding VF(n) BARs. For example, if the
170 1MB VF BAR0, the address in that VF BAR sets the base of an 8MB region.
172 is a BAR0 for one of the VFs. Note that even though the VF BAR
173 describes an 8MB region, the alignment requirement is for a single VF,
180 window with 1MB segments. VF BARs that are 1MB or larger could be
183 flexible, but it works best when all the VF BARs are the same size. If
185 the segment size matches the smallest VF BAR, which means larger VF
189 to a single PE, so it could only isolate one VF.
194 flexibility. A VF with multiple BARs would have to be in a "domain" of
205 more in the next two sections. For a given VF BAR, we need to
206 effectively reserve the entire 256 segments (256 * VF BAR size) and
207 position the VF BAR to start at the beginning of a free range of
210 The goal is of course to be able to give a separate PE for each VF.
217 SR-IOV VF BARs are all the same size.
220 than the number of M64 window segments, so if we map one VF BAR directly
234 VF(n) BAR space
243 Figure 1.0 Direct map VF(n) BAR space
245 Our current solution is to allocate 256 segments even if the VF(n) BAR
253 VF(n) BAR space + extra
262 Figure 1.1 Map VF(n) BAR space + extra
273 The PCIe SR-IOV spec requires that the base of the VF(n) BAR space be
274 aligned to the size of an individual VF BAR.
282 Therefore, the only way to control the PE# for a VF is to change the base
283 of the VF(n) BAR space in the VF BAR. If the PCI core allocates the exact
284 amount of space required for the VF(n) BAR space, the VF BAR value is fixed
287 On the other hand, if the PCI core allocates additional space, the VF BAR
288 value can be changed as long as the entire VF(n) BAR space remains inside
291 Ideally the segment size will be the same as an individual VF BAR size.
292 Then each VF will be in its own PE. The VF BARs (and therefore the PE#s)
293 are contiguous. If VF0 is in PE(x), then VF(n) is in PE(x+n). If we
296 If the segment size is smaller than the VF BAR size, it will take several
297 segments to cover a VF BAR, and a VF will be in several PEs. This is
299 choices because instead of consuming only numVFs segments, the VF(n) BAR
301 available segments for adjusting base of the VF(n) BAR space.