Lines Matching refs:stores

179 Furthermore, the stores committed by a CPU to the memory system may not be
180 perceived by the loads made by another CPU in the same order as the stores were
249  (*) Overlapping loads and stores within a particular CPU will appear to be
266      (Loads and stores overlap if they are targeted at overlapping pieces of
277  (*) It _must_not_ be assumed that independent loads and stores will be issued
389      A write barrier is a partial ordering on stores only; it is not required
393      memory system as time progresses.  All stores _before_ a write barrier
394      will occur _before_ all the stores after the write barrier.
410      only; it is not required to have any effect on stores, independent loads
414      committing sequences of stores to the memory system that the CPU being
417      load touches one of a sequence of stores from another CPU, then by the
418      time the barrier completes, the effects of all the stores prior to that
444      have any effect on stores.
460      A general memory barrier is a partial ordering over both loads and stores.
695 However, stores are not speculated.  This means that ordering -is- provided
707 the compiler might combine the store to 'b' with other stores to 'b'.
720 It is tempting to try to enforce ordering on identical stores on both
765 ordering is guaranteed only when the stores differ, for example:
817 Please note once again that the stores to 'b' differ.  If they were
869 In short, control dependencies apply only to the stores in the then-clause
881   (*) Control dependencies can order prior loads against later stores.
883       Not prior loads against later loads, nor prior stores against
885       use smp_rmb(), smp_wmb(), or, in the case of prior stores and
888   (*) If both legs of the "if" statement begin with identical stores to
889       the same variable, then those stores must be ordered, either by
891       to carry out the stores.  Please note that it is -not- sufficient
974 [!] Note that the stores before the write barrier would normally be expected to
1016 	|       |       +------+     }        requires all stores prior to the
1018 	|       |  :    +------+     }        further stores may take place
1023 	                   | Sequence in which stores are committed to the
1361 CPUs agree on the order in which all stores become visible.  However,
1377 Suppose that CPU 2's load from X returns 1, which it then stores to Y,
1473 at least aside from stores.  Therefore, the following outcome is possible:
1485 and smp_store_release() are not required to order prior stores against
1547  (*) The compiler is within its rights to reorder loads and stores
1735  (*) The compiler is within its rights to invent stores to a variable,
1803      loads followed by a pair of 32-bit stores.  This would result in
2240 order multiple stores before the wake-up with respect to loads of those stored
2367 this will ensure that the two stores issued on CPU 1 appear at the PCI bridge
2368 before either of the stores issued on CPU 2.
2539  (1) On some systems, I/O stores are not strongly ordered across all CPUs, and
2649      force stores to be ordered.
2755 their own loads and stores as if they had happened in program order.
2961      execution progress, whereas stores can often be deferred without a
2973  (*) loads and stores may be combined to improve performance when talking to