Lines Matching refs:dependency

55      - Data dependency barriers (historical).
192 There is an obvious data dependency here, as the value loaded into D depends on
397      dependency barriers; see the "SMP barrier pairing" subsection.
400  (2) Data dependency barriers.
402      A data dependency barrier is a weaker form of read barrier.  In the case
405      load will be directed), a data dependency barrier would be required to
409      A data dependency barrier is a partial ordering on interdependent loads
415      considered can then perceive.  A data dependency barrier issued by the CPU
420      dependency barrier.
425      [!] Note that the first load really has to have a _data_ dependency and
426      not a control dependency.  If the address for the second load is dependent
427      on the first load, but the dependency is through a conditional rather than
428      actually loading the address itself, then it's a _control_ dependency and
432      [!] Note that data dependency barriers should normally be paired with
438      A read barrier is a data dependency barrier plus a guarantee that all the
446      Read memory barriers imply data dependency barriers, and so can substitute
475      semantics from relying on a control dependency and smp_rmb().
565 here is the story of data-dependency barriers.
567 The usage requirements of data dependency barriers are a little subtle, and
580 There's a clear data dependency here, and it would seem that by the end of the
595 To deal with this, a data dependency barrier or better must be inserted
605 			      <data dependency barrier>
622 A data-dependency barrier is not required to order dependent writes
639 Therefore, no data-dependency barrier is required to order the read into
641 even without a data-dependency barrier:
646 of dependency ordering is to -prevent- writes to the data structure, along
652 Note well that the ordering provided by a data dependency is local to
657 The data dependency barrier is very important to the RCU system,
673 A load-load control dependency requires a full read memory barrier, not
674 simply a data dependency barrier to make it work correctly.  Consider the
679 		<data dependency barrier>  /* BUG: No data dependency!!! */
684 dependency, but rather a control dependency that the CPU may short-circuit
830 defeating control dependency:
866 A weakly ordered CPU would have no dependency of any sort between the load
874 Note well that the ordering provided by a control dependency is local
894       destroy the control dependency while respecting the letter of the
905       dependency into nonexistence.  Careful use of READ_ONCE() or
906       atomic{,64}_read() can help to preserve your control dependency.
910       of the if-statement containing the control dependency, including
913       control dependency.
934 with a data dependency barrier, a control dependency, an acquire barrier,
936 read barrier, control dependency, or a data dependency barrier pairs
955 			      <data dependency barrier>
965 			         <implicit control dependency>
975 match the loads after the read barrier or the data dependency barrier, and vice
1028 Secondly, data dependency barriers act as partial orderings on data-dependent
1074 If, however, a data dependency barrier were to be placed between the load of C
1085 				<data dependency barrier>
1299 Placing a read barrier or a data dependency barrier just before the second
1401 only the data dependency shown below:
1407 				<data dependency>	<read barrier>
1414 The key point is that although CPU 2's data dependency orders its load
1835 All memory barriers except the data dependency barriers imply a compiler
2506 CPU, that CPU's dependency ordering logic will take care of everything else.
2864 To intervene, we need to interpolate a data dependency barrier or a read
2889 Whilst most CPUs do imply a data dependency barrier on the read when a memory
3058 the data dependency barrier really becomes necessary as this synchronises both