Lines Matching refs:RELEASE

480      An ACQUIRE operation should almost always be paired with a RELEASE
484  (6) RELEASE operations.
487      memory operations before the RELEASE operation will appear to happen
488      before the RELEASE operation with respect to the other components of the
489      system. RELEASE operations include UNLOCK operations and
492      Memory operations that occur after a RELEASE operation may appear to
495      The use of ACQUIRE and RELEASE operations generally precludes the need
497      the subsection "MMIO write barrier").  In addition, a RELEASE+ACQUIRE
500      RELEASE on that same variable are guaranteed to be visible.  In other
506      RELEASE acts as a minimal "release" operation.
509 RELEASE variants in addition to fully-ordered and relaxed (no barrier
511 store, ACQUIRE semantics apply only to the load and RELEASE semantics apply
1979 In all cases there are variants on "ACQUIRE" operations and "RELEASE" operations
1990  (2) RELEASE operation implication:
1992      Memory operations issued before the RELEASE will be completed before the
1993      RELEASE operation has completed.
1995      Memory operations issued after the RELEASE may be completed before the
1996      RELEASE operation has completed.
2003  (4) ACQUIRE vs RELEASE implication:
2005      All ACQUIRE operations issued before a RELEASE operation will be
2006      completed before the RELEASE operation.
2019 An ACQUIRE followed by a RELEASE may not be assumed to be full memory barrier
2021 ACQUIRE, and an access following the RELEASE to happen before the RELEASE, and
2026 	RELEASE M
2031 	ACQUIRE M, STORE *B, STORE *A, RELEASE M
2033 When the ACQUIRE and RELEASE are a lock acquisition and release,
2035 RELEASE are to the same lock variable, but only from the perspective of
2037 RELEASE may -not- be assumed to be a full memory barrier.
2039 Similarly, the reverse case of a RELEASE followed by an ACQUIRE does
2041 critical sections corresponding to the RELEASE and the ACQUIRE can cross,
2045 	RELEASE M
2051 	ACQUIRE N, STORE *B, STORE *A, RELEASE M
2055 the RELEASE would simply complete, thereby avoiding the deadlock.
2095 	RELEASE
2101 	ACQUIRE, {*F,*A}, *E, {*C,*D}, *B, RELEASE
2107 	{*F,*A}, *B,	ACQUIRE, *C, *D,	RELEASE, *E
2108 	*A, *B, *C,	ACQUIRE, *D,		RELEASE, *E, *F
2109 	*A, *B,		ACQUIRE, *C,		RELEASE, *D, *E, *F
2110 	*B,		ACQUIRE, *C, *D,	RELEASE, {*F,*A}, *E
2118 (RELEASE equivalent) will act as compiler barriers only.  So if memory or I/O
2304 	RELEASE M			RELEASE Q
2311 	*E, ACQUIRE M, ACQUIRE Q, *G, *C, *F, *A, *B, RELEASE Q, *D, *H, RELEASE M
2316 	*A, *B or *C following RELEASE M
2318 	*E, *F or *G following RELEASE Q
2453 	RELEASE task
2495 	RELEASE task