Lines Matching refs:DMA
11 This is due to DMA constraints, which transfers only planes of 8 byte
24 capture. The new buffers are "appended" at the tail of the DMA chain, and
44 | | DMA: stop | | DMA: stop | |
51 | | DMA hotlink missed | | Capture running | |
54 | | DMA: stop | / | DMA: run | | |
56 | ^ /DMA still | | channels |
57 | | capture list / running | DMA Irq End | not |
64 | DMA: run | | DMA: run | |
73 | DMA: run | | DMA: stop |
82 - "DMA: stop" means all 3 DMA channels are stopped
83 - "DMA: run" means at least 1 DMA channel is still running
85 DMA usage
88 a) DMA flow
92 starts the DMA chain.
94 The DMA chain starts transferring data into videobuffer RAM pages.
95 When all pages are transferred, the DMA irq is raised on "ENDINTR" status
97 The DMA irq handler marks the videobuffer as "done", and removes it from
99 Meanwhile, the next videobuffer (if there is one), is transferred by DMA
101 On the DMA irq of the last videobuffer, the QCI is stopped.
103 b) DMA prepared buffer will have this structure
144 c) DMA hot chaining timeslice issue
146 As DMA chaining is done while DMA _is_ running, the linking may be done
147 while the DMA jumps from one Videobuffer to another. On the schema, that
150 - DMA chain is Videobuffer1 + Videobuffer2
152 - DMA controller finishes Videobuffer2, and DMA stops
162 +----+ +-- DMA DDADR loads DDADR_STOP
167 - the DMA irq handler is called, which terminates Videobuffer2
168 - Videobuffer3 capture is not scheduled on DMA chain (as it stopped !!!)
179 DMA DDADR still is DDADR_STOP
182 This checks if the DMA is finished and a buffer is still on the
184 and Videobuffer3 is scheduled on DMA chain.
185 - the DMA irq handler finishes
189 If DMA stops just after pxa_camera_check_link_miss() reads DDADR()
190 value, we have the guarantee that the DMA irq handler will be called back
191 when the DMA will finish the buffer, and pxa_camera_check_link_miss() will