Lines Matching refs:A
9 chipset to flush pending writes to the device before any reads are posted. A
15 A more concrete example from a hypothetical device driver::
18 CPU A: spin_lock_irqsave(&dev_lock, flags)
19 CPU A: val = readl(my_status);
20 CPU A: ...
21 CPU A: writel(newval, ring_ptr);
22 CPU A: spin_unlock_irqrestore(&dev_lock, flags)
35 CPU A: spin_lock_irqsave(&dev_lock, flags)
36 CPU A: val = readl(my_status);
37 CPU A: ...
38 CPU A: writel(newval, ring_ptr);
39 CPU A: (void)readl(safe_register); /* maybe a config register? */
40 CPU A: spin_unlock_irqrestore(&dev_lock, flags)