Lines Matching refs:GIC
3 ARM SMP cores are often associated with a GIC, providing per processor
7 Primary GIC is attached directly to the CPU and typically has PPIs and SGIs.
45 the 8 possible cpus attached to the GIC. A bit set to '1' indicated
52 - reg : Specifies base physical address(s) and size of the GIC registers. The
53 first region is the GIC distributor register base and size. The 2nd region is
54 the GIC cpu interface register base and size.
58 secondary GICs, or VGIC maintenance interrupt on primary GIC (see
62 regions, used when the GIC doesn't have banked registers. The offset is
67 - clock-names : List of names for the GIC clock input(s). Valid clock names
68 depend on the GIC variant:
76 the power controller specified by phandle, used when the GIC
92 * GIC virtualization extensions (VGIC)
95 properties must be described (they only exist if the GIC is the
101 size of the VGIC registers. The first additional region is the GIC
103 region is the GIC virtual cpu interface register base and size.
123 Certain revisions of GIC-400 supports MSI/MSI-x via V2M register frame(s).