Lines Matching refs:HDMI
35 HDMI Encoder
38 The HDMI Encoder supports the HDMI video and audio outputs, and does
48 - clocks: phandles to the clocks feeding the HDMI encoder
49 * ahb: the HDMI interface clock
50 * mod: the HDMI module clock
51 * ddc: the HDMI ddc clock (A31 only)
55 - resets: phandle to the reset control for the HDMI encoder (A31 only)
56 - dmas: phandles to the DMA channels used by the HDMI encoder
65 output, usually to an HDMI connector.
67 DWC HDMI TX Encoder
70 The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
73 These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
83 - interrupts: HDMI interrupt number
84 - clocks: phandles to the clocks feeding the HDMI encoder
85 * iahb: the HDMI bus clock
86 * isfr: the HDMI register clock
91 - phys: phandle to the DWC HDMI PHY
97 output, usually to an HDMI connector.
99 DWC HDMI PHY
108 - clocks: phandles to the clocks feeding the HDMI PHY
109 * bus: the HDMI PHY interface clock
110 * mod: the HDMI PHY module clock
115 H3 and A64 HDMI PHY require additional clocks:
175 require another controller (TV Encoder, HDMI, etc.). The endpoints
197 relationships between mixers and TCONs, selects source TCON for HDMI, muxes
211 | TCON-TOP - HDMI
242 * port 4 is input for HDMI mux
243 * port 5 is output for HDMI mux
244 All output endpoints for mixer muxes and input endpoints for HDMI mux should
246 (0-3 for mixer muxes and 0-1 for HDMI mux). All ports should have only one