Lines Matching refs:DSI
1 Qualcomm Technologies Inc. adreno/snapdragon DSI output
3 DSI Controller:
10 - interrupts: The interrupt signal from the DSI block.
27 by a DSI PHY block. See [1] for details on clock bindings.
31 - phys: phandle to DSI PHY device node
34 - ports: Contains 2 DSI controller ports as child nodes. Each port contains
38 - panel@0: Node of panel connected to this DSI controller.
40 - qcom,dual-dsi-mode: Boolean value indicating if the DSI controller is
41 driving a panel which needs 2 DSI links.
42 - qcom,master-dsi: Boolean value indicating if the DSI controller is driving
43 the master link of the 2-DSI panel.
44 - qcom,sync-dual-dsi: Boolean value indicating if the DSI controller is
45 driving a 2-DSI panel whose 2 links need receive command simultaneously.
49 - ports: contains DSI controller input and output ports as children, each
52 DSI Endpoint properties:
57 - data-lanes: this describes how the physical DSI data lanes are mapped
82 DSI PHY:
95 For DSI 28nm HPM/LP/8960 PHYs and 20nm PHY:
99 For DSI 14nm and 10nm PHYs:
103 - clock-cells: Must be 1. The DSI PHY block acts as a clock provider, creating