Lines Matching refs:HDMI
1 Amlogic specific extensions to the Synopsys Designware HDMI Controller
5 - A Synopsys DesignWare HDMI Controller IP
7 - A custom HDMI PHY in order to convert video to TMDS signal
9 | HDMI TOP |<= HPD
12 | Synopsys HDMI | HDMI PHY |=> TMDS
16 The HDMI TOP block only supports HPD sensing.
17 The Synopsys HDMI Controller interrupt is routed through the
19 Communication to the TOP Block and the Synopsys HDMI Controller is done
21 The HDMI PHY is configured by registers in the HHI register block.
23 Pixel data arrives in 4:4:4 format from the VENC block and the VPU HDMI mux
28 DVI timings for the HDMI controller.
31 HDMI TX IP version 2.01a with HDCP and I2C & S/PDIF
41 - interrupts: The HDMI interrupt number
42 - clocks, clock-names : must have the phandles to the HDMI iahb and isfr clocks,
46 - resets, resets-names: must have the phandles to the HDMI apb, glue and phy
52 - hdmi-supply: Optional phandle to an external 5V regulator to power the HDMI
57 The connections to the HDMI ports are modeled using the OF graph
61 corresponding to each HDMI output and input.