Lines Matching refs:must
48 The device tree blob (dtb) must be placed on an 8-byte boundary and must
50 using blocks of up to 2 megabytes in size, it must not be placed within
51 any 2M region which must be mapped with any specific attributes.
101 little-endian and must be respected. Where image_size is zero,
125 The Image must be placed text_offset bytes from a 2MB aligned base
129 At least image_size bytes from the start of the image must be free for
135 If an initrd/initramfs is passed to the kernel at boot, it must reside
144 Before jumping into the kernel, the following conditions must be met:
157 All forms of interrupts must be masked in PSTATE.DAIF (Debug, SError,
159 The CPU must be in either EL2 (RECOMMENDED in order to have access to
163 The MMU must be off.
165 The address range corresponding to the loaded kernel image must be
170 operations must be configured and may be enabled.
172 operations (not recommended) must be configured and disabled.
175 CNTFRQ must be programmed with the timer frequency and CNTVOFF must
177 kernel at EL1, CNTHCTL_EL2 must have EL1PCTEN (bit 0) set where
181 All CPUs to be booted by the kernel must be part of the same coherency
188 the kernel image will be entered must be initialised by software at a
193 ICC_SRE_EL3.Enable (bit 3) must be initialiased to 0b1.
194 ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b1.
196 ICC.SRE_EL2.Enable (bit 3) must be initialised to 0b1
197 ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b1.
198 - The DT or ACPI tables must describe a GICv3 interrupt controller.
203 ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b0.
205 ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b0.
206 - The DT or ACPI tables must describe a GICv2 interrupt controller.
209 timers, coherency and system registers apply to all CPUs. All CPUs must
215 - The primary CPU must jump directly to the first instruction of the
216 kernel image. The device tree blob passed by this CPU must contain
223 - CPUs with a "spin-table" enable-method must have a 'cpu-release-addr'
229 device tree) polling their cpu-release-addr location, which must be
233 cpu-release-addr returns a non-zero value, the CPU must jump to this
235 value, so CPUs must convert the read value to their native endianness